1050a99a6SPankaj Gupta /* 2050a99a6SPankaj Gupta * Copyright 2020-2021 NXP 3050a99a6SPankaj Gupta * 4050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5050a99a6SPankaj Gupta * 6050a99a6SPankaj Gupta */ 7050a99a6SPankaj Gupta 8050a99a6SPankaj Gupta #ifndef DCFG_LSCH3_H 9050a99a6SPankaj Gupta #define DCFG_LSCH3_H 10050a99a6SPankaj Gupta 11050a99a6SPankaj Gupta /* dcfg block register offsets and bitfields */ 12050a99a6SPankaj Gupta #define DCFG_PORSR1_OFFSET 0x00 13050a99a6SPankaj Gupta 14050a99a6SPankaj Gupta #define DCFG_DEVDISR1_OFFSET 0x70 15050a99a6SPankaj Gupta #define DCFG_DEVDISR1_SEC (1 << 22) 16050a99a6SPankaj Gupta 17050a99a6SPankaj Gupta #define DCFG_DEVDISR2_OFFSET 0x74 18050a99a6SPankaj Gupta 19050a99a6SPankaj Gupta #define DCFG_DEVDISR3_OFFSET 0x78 20050a99a6SPankaj Gupta #define DCFG_DEVDISR3_QBMAIN (1 << 12) 21050a99a6SPankaj Gupta 22050a99a6SPankaj Gupta #define DCFG_DEVDISR4_OFFSET 0x7C 23050a99a6SPankaj Gupta #define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5) 24050a99a6SPankaj Gupta 25050a99a6SPankaj Gupta #define DCFG_DEVDISR5_OFFSET 0x80 26050a99a6SPankaj Gupta #define DISR5_DDRC1_MASK 0x1 27050a99a6SPankaj Gupta #define DISR5_DDRC2_MASK 0x2 28050a99a6SPankaj Gupta #define DISR5_OCRAM_MASK 0x1000 29050a99a6SPankaj Gupta #define DEVDISR5_MASK_ALL_MEM 0x00001003 30050a99a6SPankaj Gupta #define DEVDISR5_MASK_DDR 0x00000003 31050a99a6SPankaj Gupta #define DEVDISR5_MASK_DBG 0x00000400 32050a99a6SPankaj Gupta 33050a99a6SPankaj Gupta #define DCFG_DEVDISR6_OFFSET 0x84 34050a99a6SPankaj Gupta //#define DEVDISR6_MASK 0x00000001 35050a99a6SPankaj Gupta 36050a99a6SPankaj Gupta #define DCFG_COREDISR_OFFSET 0x94 37050a99a6SPankaj Gupta 38050a99a6SPankaj Gupta #define DCFG_SVR_OFFSET 0x0A4 39050a99a6SPankaj Gupta #define SVR_MFR_ID_MASK 0xF0000000 40050a99a6SPankaj Gupta #define SVR_MFR_ID_SHIFT 28 41050a99a6SPankaj Gupta #define SVR_FAMILY_MASK 0xF000000 42050a99a6SPankaj Gupta #define SVR_FAMILY_SHIFT 24 43050a99a6SPankaj Gupta #define SVR_DEV_ID_MASK 0x3F0000 44050a99a6SPankaj Gupta #define SVR_DEV_ID_SHIFT 16 45050a99a6SPankaj Gupta #define SVR_PERSONALITY_MASK 0x3E00 46050a99a6SPankaj Gupta #define SVR_PERSONALITY_SHIFT 9 47050a99a6SPankaj Gupta #define SVR_SEC_MASK 0x100 48050a99a6SPankaj Gupta #define SVR_SEC_SHIFT 8 49050a99a6SPankaj Gupta #define SVR_MAJ_VER_MASK 0xF0 50050a99a6SPankaj Gupta #define SVR_MAJ_VER_SHIFT 4 51050a99a6SPankaj Gupta #define SVR_MIN_VER_MASK 0xF 52050a99a6SPankaj Gupta 53050a99a6SPankaj Gupta #define RCWSR0_OFFSET 0x100 54050a99a6SPankaj Gupta #define RCWSR0_SYS_PLL_RAT_SHIFT 2 55050a99a6SPankaj Gupta #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 56050a99a6SPankaj Gupta #define RCWSR0_MEM_PLL_RAT_SHIFT 10 57050a99a6SPankaj Gupta #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 58050a99a6SPankaj Gupta #define RCWSR0_MEM2_PLL_RAT_SHIFT 18 59050a99a6SPankaj Gupta #define RCWSR0_MEM2_PLL_RAT_MASK 0x3f 60050a99a6SPankaj Gupta 61050a99a6SPankaj Gupta #define RCWSR5_OFFSET 0x110 62050a99a6SPankaj Gupta #define RCWSR9_OFFSET 0x120 63050a99a6SPankaj Gupta #define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET 64050a99a6SPankaj Gupta #define RCWSR_SBEN_MASK 0x1 65050a99a6SPankaj Gupta #define RCWSR_SBEN_SHIFT 10 66050a99a6SPankaj Gupta 67050a99a6SPankaj Gupta #define RCW_SR27_OFFSET 0x168 68050a99a6SPankaj Gupta /* DCFG register to dump error code */ 69050a99a6SPankaj Gupta #define DCFG_SCRATCH4_OFFSET 0x20C 70050a99a6SPankaj Gupta #define DCFG_SCRATCHRW5_OFFSET 0x210 71050a99a6SPankaj Gupta #define DCFG_SCRATCHRW6_OFFSET 0x214 72050a99a6SPankaj Gupta #define DCFG_SCRATCHRW7_OFFSET 0x218 73050a99a6SPankaj Gupta #define DCFG_BOOTLOCPTRL_OFFSET 0x400 74050a99a6SPankaj Gupta #define DCFG_BOOTLOCPTRH_OFFSET 0x404 75050a99a6SPankaj Gupta #define DCFG_COREDISABLEDSR_OFFSET 0x990 76050a99a6SPankaj Gupta 77*6c5d140eSJiafei Pan /* Reset module bit field */ 78*6c5d140eSJiafei Pan #define RSTCR_RESET_REQ 0x2 79*6c5d140eSJiafei Pan 80050a99a6SPankaj Gupta #endif /* DCFG_LSCH3_H */ 81