1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2020-2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #ifndef DCFG_LSCH3_H 9*050a99a6SPankaj Gupta #define DCFG_LSCH3_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta /* dcfg block register offsets and bitfields */ 12*050a99a6SPankaj Gupta #define DCFG_PORSR1_OFFSET 0x00 13*050a99a6SPankaj Gupta 14*050a99a6SPankaj Gupta #define DCFG_DEVDISR1_OFFSET 0x70 15*050a99a6SPankaj Gupta #define DCFG_DEVDISR1_SEC (1 << 22) 16*050a99a6SPankaj Gupta 17*050a99a6SPankaj Gupta #define DCFG_DEVDISR2_OFFSET 0x74 18*050a99a6SPankaj Gupta 19*050a99a6SPankaj Gupta #define DCFG_DEVDISR3_OFFSET 0x78 20*050a99a6SPankaj Gupta #define DCFG_DEVDISR3_QBMAIN (1 << 12) 21*050a99a6SPankaj Gupta 22*050a99a6SPankaj Gupta #define DCFG_DEVDISR4_OFFSET 0x7C 23*050a99a6SPankaj Gupta #define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5) 24*050a99a6SPankaj Gupta 25*050a99a6SPankaj Gupta #define DCFG_DEVDISR5_OFFSET 0x80 26*050a99a6SPankaj Gupta #define DISR5_DDRC1_MASK 0x1 27*050a99a6SPankaj Gupta #define DISR5_DDRC2_MASK 0x2 28*050a99a6SPankaj Gupta #define DISR5_OCRAM_MASK 0x1000 29*050a99a6SPankaj Gupta #define DEVDISR5_MASK_ALL_MEM 0x00001003 30*050a99a6SPankaj Gupta #define DEVDISR5_MASK_DDR 0x00000003 31*050a99a6SPankaj Gupta #define DEVDISR5_MASK_DBG 0x00000400 32*050a99a6SPankaj Gupta 33*050a99a6SPankaj Gupta #define DCFG_DEVDISR6_OFFSET 0x84 34*050a99a6SPankaj Gupta //#define DEVDISR6_MASK 0x00000001 35*050a99a6SPankaj Gupta 36*050a99a6SPankaj Gupta #define DCFG_COREDISR_OFFSET 0x94 37*050a99a6SPankaj Gupta 38*050a99a6SPankaj Gupta #define DCFG_SVR_OFFSET 0x0A4 39*050a99a6SPankaj Gupta #define SVR_MFR_ID_MASK 0xF0000000 40*050a99a6SPankaj Gupta #define SVR_MFR_ID_SHIFT 28 41*050a99a6SPankaj Gupta #define SVR_FAMILY_MASK 0xF000000 42*050a99a6SPankaj Gupta #define SVR_FAMILY_SHIFT 24 43*050a99a6SPankaj Gupta #define SVR_DEV_ID_MASK 0x3F0000 44*050a99a6SPankaj Gupta #define SVR_DEV_ID_SHIFT 16 45*050a99a6SPankaj Gupta #define SVR_PERSONALITY_MASK 0x3E00 46*050a99a6SPankaj Gupta #define SVR_PERSONALITY_SHIFT 9 47*050a99a6SPankaj Gupta #define SVR_SEC_MASK 0x100 48*050a99a6SPankaj Gupta #define SVR_SEC_SHIFT 8 49*050a99a6SPankaj Gupta #define SVR_MAJ_VER_MASK 0xF0 50*050a99a6SPankaj Gupta #define SVR_MAJ_VER_SHIFT 4 51*050a99a6SPankaj Gupta #define SVR_MIN_VER_MASK 0xF 52*050a99a6SPankaj Gupta 53*050a99a6SPankaj Gupta #define RCWSR0_OFFSET 0x100 54*050a99a6SPankaj Gupta #define RCWSR0_SYS_PLL_RAT_SHIFT 2 55*050a99a6SPankaj Gupta #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 56*050a99a6SPankaj Gupta #define RCWSR0_MEM_PLL_RAT_SHIFT 10 57*050a99a6SPankaj Gupta #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 58*050a99a6SPankaj Gupta #define RCWSR0_MEM2_PLL_RAT_SHIFT 18 59*050a99a6SPankaj Gupta #define RCWSR0_MEM2_PLL_RAT_MASK 0x3f 60*050a99a6SPankaj Gupta 61*050a99a6SPankaj Gupta #define RCWSR5_OFFSET 0x110 62*050a99a6SPankaj Gupta #define RCWSR9_OFFSET 0x120 63*050a99a6SPankaj Gupta #define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET 64*050a99a6SPankaj Gupta #define RCWSR_SBEN_MASK 0x1 65*050a99a6SPankaj Gupta #define RCWSR_SBEN_SHIFT 10 66*050a99a6SPankaj Gupta 67*050a99a6SPankaj Gupta #define RCW_SR27_OFFSET 0x168 68*050a99a6SPankaj Gupta /* DCFG register to dump error code */ 69*050a99a6SPankaj Gupta #define DCFG_SCRATCH4_OFFSET 0x20C 70*050a99a6SPankaj Gupta #define DCFG_SCRATCHRW5_OFFSET 0x210 71*050a99a6SPankaj Gupta #define DCFG_SCRATCHRW6_OFFSET 0x214 72*050a99a6SPankaj Gupta #define DCFG_SCRATCHRW7_OFFSET 0x218 73*050a99a6SPankaj Gupta #define DCFG_BOOTLOCPTRL_OFFSET 0x400 74*050a99a6SPankaj Gupta #define DCFG_BOOTLOCPTRH_OFFSET 0x404 75*050a99a6SPankaj Gupta #define DCFG_COREDISABLEDSR_OFFSET 0x990 76*050a99a6SPankaj Gupta 77*050a99a6SPankaj Gupta #endif /* DCFG_LSCH3_H */ 78