1050a99a6SPankaj Gupta /* 2050a99a6SPankaj Gupta * Copyright 2020-2021 NXP 3050a99a6SPankaj Gupta * 4050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5050a99a6SPankaj Gupta * 6050a99a6SPankaj Gupta */ 7050a99a6SPankaj Gupta 8050a99a6SPankaj Gupta #ifndef DCFG_LSCH2_H 9050a99a6SPankaj Gupta #define DCFG_LSCH2_H 10050a99a6SPankaj Gupta 11050a99a6SPankaj Gupta /* dcfg block register offsets and bitfields */ 12050a99a6SPankaj Gupta #define DCFG_PORSR1_OFFSET 0x00 13050a99a6SPankaj Gupta #define DCFG_DEVDISR1_OFFSET 0x070 14*1b29fe53SJiafei Pan #define DCFG_DEVDISR2_OFFSET 0x074 15*1b29fe53SJiafei Pan #define DCFG_DEVDISR3_OFFSET 0x078 16050a99a6SPankaj Gupta #define DCFG_DEVDISR4_OFFSET 0x07C 17050a99a6SPankaj Gupta #define DCFG_DEVDISR5_OFFSET 0x080 18050a99a6SPankaj Gupta #define DCFG_COREDISR_OFFSET 0x094 19050a99a6SPankaj Gupta #define RCWSR0_OFFSET 0x100 20050a99a6SPankaj Gupta #define RCWSR5_OFFSET 0x118 21050a99a6SPankaj Gupta #define DCFG_BOOTLOCPTRL_OFFSET 0x400 22050a99a6SPankaj Gupta #define DCFG_BOOTLOCPTRH_OFFSET 0x404 23050a99a6SPankaj Gupta #define DCFG_COREDISABLEDSR_OFFSET 0x990 24050a99a6SPankaj Gupta #define DCFG_SCRATCH4_OFFSET 0x20C 25050a99a6SPankaj Gupta #define DCFG_SVR_OFFSET 0x0A4 26050a99a6SPankaj Gupta #define DCFG_BRR_OFFSET 0x0E4 27050a99a6SPankaj Gupta 28050a99a6SPankaj Gupta #define DCFG_RSTCR_OFFSET 0x0B0 29050a99a6SPankaj Gupta #define RSTCR_RESET_REQ 0x2 30050a99a6SPankaj Gupta 31050a99a6SPankaj Gupta #define DCFG_RSTRQSR1_OFFSET 0x0C8 32050a99a6SPankaj Gupta #define DCFG_RSTRQMR1_OFFSET 0x0C0 33050a99a6SPankaj Gupta 34*1b29fe53SJiafei Pan /* PORSR1 bit mask */ 35*1b29fe53SJiafei Pan #define PORSR1_RCW_MASK 0xff800000 36*1b29fe53SJiafei Pan #define PORSR1_RCW_SHIFT 23 37*1b29fe53SJiafei Pan 38050a99a6SPankaj Gupta /* DCFG DCSR Macros */ 39050a99a6SPankaj Gupta #define DCFG_DCSR_PORCR1_OFFSET 0x0 40050a99a6SPankaj Gupta 41050a99a6SPankaj Gupta #define SVR_MFR_ID_MASK 0xF0000000 42050a99a6SPankaj Gupta #define SVR_MFR_ID_SHIFT 28 4308695df9SJiafei Pan #define SVR_DEV_ID_MASK 0xFFF0000 44050a99a6SPankaj Gupta #define SVR_DEV_ID_SHIFT 16 4508695df9SJiafei Pan #define SVR_PERSONALITY_MASK 0xFF00 4608695df9SJiafei Pan #define SVR_PERSONALITY_SHIFT 8 47050a99a6SPankaj Gupta #define SVR_SEC_MASK 0x100 48050a99a6SPankaj Gupta #define SVR_SEC_SHIFT 8 49050a99a6SPankaj Gupta #define SVR_MAJ_VER_MASK 0xF0 50050a99a6SPankaj Gupta #define SVR_MAJ_VER_SHIFT 4 51050a99a6SPankaj Gupta #define SVR_MIN_VER_MASK 0xF 52*1b29fe53SJiafei Pan #define SVR_MINOR_VER_0 0x00 53*1b29fe53SJiafei Pan #define SVR_MINOR_VER_1 0x01 54050a99a6SPankaj Gupta 55050a99a6SPankaj Gupta #define DISR5_DDRC1_MASK 0x1 56050a99a6SPankaj Gupta #define DISR5_OCRAM_MASK 0x40 57050a99a6SPankaj Gupta 58050a99a6SPankaj Gupta /* DCFG regsiters bit masks */ 59050a99a6SPankaj Gupta #define RCWSR0_SYS_PLL_RAT_SHIFT 25 60050a99a6SPankaj Gupta #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 61050a99a6SPankaj Gupta #define RCWSR0_MEM_PLL_RAT_SHIFT 16 62050a99a6SPankaj Gupta #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 63050a99a6SPankaj Gupta #define RCWSR0_MEM2_PLL_RAT_SHIFT 18 64050a99a6SPankaj Gupta #define RCWSR0_MEM2_PLL_RAT_MASK 0x3f 65050a99a6SPankaj Gupta 66050a99a6SPankaj Gupta #define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET 67050a99a6SPankaj Gupta #define RCWSR_SBEN_MASK 0x1 68050a99a6SPankaj Gupta #define RCWSR_SBEN_SHIFT 21 69050a99a6SPankaj Gupta 70050a99a6SPankaj Gupta /* RCW SRC NAND */ 71050a99a6SPankaj Gupta #define RCW_SRC_NAND_MASK (0x100) 72050a99a6SPankaj Gupta #define RCW_SRC_NAND_VAL (0x100) 73050a99a6SPankaj Gupta #define NAND_RESERVED_MASK (0xFC) 74050a99a6SPankaj Gupta #define NAND_RESERVED_1 (0x0) 75050a99a6SPankaj Gupta #define NAND_RESERVED_2 (0x80) 76050a99a6SPankaj Gupta 77050a99a6SPankaj Gupta /* RCW SRC NOR */ 78050a99a6SPankaj Gupta #define RCW_SRC_NOR_MASK (0x1F0) 79050a99a6SPankaj Gupta #define NOR_8B_VAL (0x10) 80050a99a6SPankaj Gupta #define NOR_16B_VAL (0x20) 81050a99a6SPankaj Gupta #define SD_VAL (0x40) 82050a99a6SPankaj Gupta #define QSPI_VAL1 (0x44) 83050a99a6SPankaj Gupta #define QSPI_VAL2 (0x45) 84050a99a6SPankaj Gupta 85050a99a6SPankaj Gupta #endif /* DCFG_LSCH2_H */ 86