1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2018-2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #ifndef DCFG_H 9*050a99a6SPankaj Gupta #define DCFG_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta #include <endian.h> 12*050a99a6SPankaj Gupta 13*050a99a6SPankaj Gupta #if defined(CONFIG_CHASSIS_2) 14*050a99a6SPankaj Gupta #include <dcfg_lsch2.h> 15*050a99a6SPankaj Gupta #elif defined(CONFIG_CHASSIS_3_2) 16*050a99a6SPankaj Gupta #include <dcfg_lsch3.h> 17*050a99a6SPankaj Gupta #endif 18*050a99a6SPankaj Gupta 19*050a99a6SPankaj Gupta #ifdef NXP_GUR_BE 20*050a99a6SPankaj Gupta #define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 21*050a99a6SPankaj Gupta #define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 22*050a99a6SPankaj Gupta #elif defined(NXP_GUR_LE) 23*050a99a6SPankaj Gupta #define gur_in32(a) mmio_read_32((uintptr_t)(a)) 24*050a99a6SPankaj Gupta #define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v) 25*050a99a6SPankaj Gupta #else 26*050a99a6SPankaj Gupta #error Please define CCSR GUR register endianness 27*050a99a6SPankaj Gupta #endif 28*050a99a6SPankaj Gupta 29*050a99a6SPankaj Gupta typedef struct { 30*050a99a6SPankaj Gupta bool is_populated; 31*050a99a6SPankaj Gupta uint8_t mfr_id; 32*050a99a6SPankaj Gupta #if defined(CONFIG_CHASSIS_3_2) 33*050a99a6SPankaj Gupta uint8_t family; 34*050a99a6SPankaj Gupta uint8_t dev_id; 35*050a99a6SPankaj Gupta #endif 36*050a99a6SPankaj Gupta uint8_t personality; 37*050a99a6SPankaj Gupta bool sec_enabled; 38*050a99a6SPankaj Gupta uint8_t maj_ver; 39*050a99a6SPankaj Gupta uint8_t min_ver; 40*050a99a6SPankaj Gupta } soc_info_t; 41*050a99a6SPankaj Gupta 42*050a99a6SPankaj Gupta typedef struct { 43*050a99a6SPankaj Gupta bool is_populated; 44*050a99a6SPankaj Gupta uint8_t ocram_present; 45*050a99a6SPankaj Gupta uint8_t ddrc1_present; 46*050a99a6SPankaj Gupta #if defined(CONFIG_CHASSIS_3_2) 47*050a99a6SPankaj Gupta uint8_t ddrc2_present; 48*050a99a6SPankaj Gupta #endif 49*050a99a6SPankaj Gupta } devdisr5_info_t; 50*050a99a6SPankaj Gupta 51*050a99a6SPankaj Gupta typedef struct { 52*050a99a6SPankaj Gupta uint32_t porsr1; 53*050a99a6SPankaj Gupta uintptr_t g_nxp_dcfg_addr; 54*050a99a6SPankaj Gupta unsigned long nxp_sysclk_freq; 55*050a99a6SPankaj Gupta unsigned long nxp_ddrclk_freq; 56*050a99a6SPankaj Gupta unsigned int nxp_plat_clk_divider; 57*050a99a6SPankaj Gupta } dcfg_init_info_t; 58*050a99a6SPankaj Gupta 59*050a99a6SPankaj Gupta 60*050a99a6SPankaj Gupta struct sysinfo { 61*050a99a6SPankaj Gupta unsigned long freq_platform; 62*050a99a6SPankaj Gupta unsigned long freq_ddr_pll0; 63*050a99a6SPankaj Gupta unsigned long freq_ddr_pll1; 64*050a99a6SPankaj Gupta }; 65*050a99a6SPankaj Gupta 66*050a99a6SPankaj Gupta int get_clocks(struct sysinfo *sys); 67*050a99a6SPankaj Gupta 68*050a99a6SPankaj Gupta /* Read the PORSR1 register */ 69*050a99a6SPankaj Gupta uint32_t read_reg_porsr1(void); 70*050a99a6SPankaj Gupta 71*050a99a6SPankaj Gupta /******************************************************************************* 72*050a99a6SPankaj Gupta * Returns true if secur eboot is enabled on board 73*050a99a6SPankaj Gupta * mode = 0 (development mode - sb_en = 1) 74*050a99a6SPankaj Gupta * mode = 1 (production mode - ITS = 1) 75*050a99a6SPankaj Gupta ******************************************************************************/ 76*050a99a6SPankaj Gupta bool check_boot_mode_secure(uint32_t *mode); 77*050a99a6SPankaj Gupta 78*050a99a6SPankaj Gupta const soc_info_t *get_soc_info(); 79*050a99a6SPankaj Gupta const devdisr5_info_t *get_devdisr5_info(); 80*050a99a6SPankaj Gupta 81*050a99a6SPankaj Gupta void dcfg_init(dcfg_init_info_t *dcfg_init_data); 82*050a99a6SPankaj Gupta bool is_sec_enabled(void); 83*050a99a6SPankaj Gupta 84*050a99a6SPankaj Gupta void error_handler(int error_code); 85*050a99a6SPankaj Gupta #endif /* DCFG_H */ 86