1050a99a6SPankaj Gupta /* 2050a99a6SPankaj Gupta * Copyright 2021 NXP 3050a99a6SPankaj Gupta * 4050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5050a99a6SPankaj Gupta * 6050a99a6SPankaj Gupta */ 7050a99a6SPankaj Gupta 8050a99a6SPankaj Gupta #ifndef CSU_H 9050a99a6SPankaj Gupta #define CSU_H 10050a99a6SPankaj Gupta 11050a99a6SPankaj Gupta #define CSU_SEC_ACCESS_REG_OFFSET (0x0021CU) 12*ec5fc501SJiafei Pan /* Bit mask */ 13*ec5fc501SJiafei Pan #define TZASC_BYPASS_MUX_DISABLE (0x4U) 14050a99a6SPankaj Gupta 15050a99a6SPankaj Gupta /* Macros defining access permissions to configure 16050a99a6SPankaj Gupta * the regions controlled by Central Security Unit. 17050a99a6SPankaj Gupta */ 18050a99a6SPankaj Gupta enum csu_cslx_access { 19050a99a6SPankaj Gupta CSU_NS_SUP_R = (0x8U), 20050a99a6SPankaj Gupta CSU_NS_SUP_W = (0x80U), 21050a99a6SPankaj Gupta CSU_NS_SUP_RW = (0x88U), 22050a99a6SPankaj Gupta CSU_NS_USER_R = (0x4U), 23050a99a6SPankaj Gupta CSU_NS_USER_W = (0x40U), 24050a99a6SPankaj Gupta CSU_NS_USER_RW = (0x44U), 25050a99a6SPankaj Gupta CSU_S_SUP_R = (0x2U), 26050a99a6SPankaj Gupta CSU_S_SUP_W = (0x20U), 27050a99a6SPankaj Gupta CSU_S_SUP_RW = (0x22U), 28050a99a6SPankaj Gupta CSU_S_USER_R = (0x1U), 29050a99a6SPankaj Gupta CSU_S_USER_W = (0x10U), 30050a99a6SPankaj Gupta CSU_S_USER_RW = (0x11U), 31050a99a6SPankaj Gupta CSU_ALL_RW = (0xffU), 32050a99a6SPankaj Gupta }; 33050a99a6SPankaj Gupta 34050a99a6SPankaj Gupta struct csu_ns_dev_st { 35050a99a6SPankaj Gupta uintptr_t ind; 36050a99a6SPankaj Gupta uint32_t val; 37050a99a6SPankaj Gupta }; 38050a99a6SPankaj Gupta 39050a99a6SPankaj Gupta void enable_layerscape_ns_access(struct csu_ns_dev_st *csu_ns_dev, 40050a99a6SPankaj Gupta uint32_t num, uintptr_t nxp_csu_addr); 41050a99a6SPankaj Gupta 42050a99a6SPankaj Gupta #endif 43