1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MMC_H 8 #define MMC_H 9 10 #include <stdint.h> 11 12 #include <lib/utils_def.h> 13 14 #define MMC_BLOCK_SIZE U(512) 15 #define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1)) 16 #define MMC_BOOT_CLK_RATE (400 * 1000) 17 18 #define MMC_CMD(_x) U(_x) 19 20 #define MMC_ACMD(_x) U(_x) 21 22 #define OCR_POWERUP BIT_32(31U) 23 #define OCR_HCS BIT_32(30U) 24 #define OCR_BYTE_MODE (U(0) << 29U) 25 #define OCR_SECTOR_MODE (U(2) << 29U) 26 #define OCR_ACCESS_MODE_MASK (U(3) << 29U) 27 #define OCR_3_5_3_6 BIT_32(23U) 28 #define OCR_3_4_3_5 BIT_32(22U) 29 #define OCR_3_3_3_4 BIT_32(21U) 30 #define OCR_3_2_3_3 BIT_32(20U) 31 #define OCR_3_1_3_2 BIT_32(19U) 32 #define OCR_3_0_3_1 BIT_32(18U) 33 #define OCR_2_9_3_0 BIT_32(17U) 34 #define OCR_2_8_2_9 BIT_32(16U) 35 #define OCR_2_7_2_8 BIT_32(15U) 36 #define OCR_VDD_MIN_2V7 GENMASK_32(23U, 15U) 37 #define OCR_VDD_MIN_2V0 GENMASK_32(14U, 8U) 38 #define OCR_VDD_MIN_1V7 BIT_32(7U) 39 40 #define MMC_RSP_48 BIT_32(0U) 41 #define MMC_RSP_136 BIT_32(1U) /* 136 bit response */ 42 #define MMC_RSP_CRC BIT_32(2U) /* expect valid crc */ 43 #define MMC_RSP_CMD_IDX BIT_32(3U) /* response contains cmd idx */ 44 #define MMC_RSP_BUSY BIT_32(4U) /* device may be busy */ 45 46 /* JEDEC 4.51 chapter 6.12 */ 47 #define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC) 48 #define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY) 49 #define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC) 50 #define MMC_RESPONSE_R3 (MMC_RSP_48) 51 #define MMC_RESPONSE_R4 (MMC_RSP_48) 52 #define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 53 #define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 54 #define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 55 #define MMC_RESPONSE_NONE 0U 56 57 /* Value randomly chosen for eMMC RCA, it should be > 1 */ 58 #define MMC_FIX_RCA 6 59 #define RCA_SHIFT_OFFSET 16 60 61 #define CMD_EXTCSD_PARTITION_CONFIG 179 62 #define CMD_EXTCSD_BUS_WIDTH 183 63 #define CMD_EXTCSD_HS_TIMING 185 64 #define CMD_EXTCSD_PART_SWITCH_TIME 199 65 #define CMD_EXTCSD_SEC_CNT 212 66 #define CMD_EXTCSD_BOOT_SIZE_MULT 226 67 68 #define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0) 69 #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) 70 #define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0) 71 #define PART_CFG_BOOT_PARTITION_NO_ACCESS U(0) 72 #define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3) 73 #define PART_CFG_BOOT_PART_EN_SHIFT 3 74 #define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \ 75 PART_CFG_BOOT_PART_EN_SHIFT) 76 77 /* Values in EXT CSD register */ 78 #define MMC_BUS_WIDTH_1 U(0) 79 #define MMC_BUS_WIDTH_4 U(1) 80 #define MMC_BUS_WIDTH_8 U(2) 81 #define MMC_BUS_WIDTH_DDR_4 U(5) 82 #define MMC_BUS_WIDTH_DDR_8 U(6) 83 #define MMC_BOOT_MODE_BACKWARD (U(0) << 3) 84 #define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) 85 #define MMC_BOOT_MODE_DDR (U(2) << 3) 86 87 #define EXTCSD_SET_CMD (U(0) << 24) 88 #define EXTCSD_SET_BITS (U(1) << 24) 89 #define EXTCSD_CLR_BITS (U(2) << 24) 90 #define EXTCSD_WRITE_BYTES (U(3) << 24) 91 #define EXTCSD_CMD(x) (((x) & 0xff) << 16) 92 #define EXTCSD_VALUE(x) (((x) & 0xff) << 8) 93 #define EXTCSD_CMD_SET_NORMAL U(1) 94 95 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) 96 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) 97 #define CSD_TRAN_SPEED_MULT_SHIFT 3 98 99 #define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) 100 #define STATUS_READY_FOR_DATA BIT(8) 101 #define STATUS_SWITCH_ERROR BIT(7) 102 #define MMC_GET_STATE(x) (((x) >> 9) & 0xf) 103 #define MMC_STATE_IDLE 0 104 #define MMC_STATE_READY 1 105 #define MMC_STATE_IDENT 2 106 #define MMC_STATE_STBY 3 107 #define MMC_STATE_TRAN 4 108 #define MMC_STATE_DATA 5 109 #define MMC_STATE_RCV 6 110 #define MMC_STATE_PRG 7 111 #define MMC_STATE_DIS 8 112 #define MMC_STATE_BTST 9 113 #define MMC_STATE_SLP 10 114 115 #define MMC_FLAG_CMD23 (U(1) << 0) 116 #define MMC_FLAG_SD_CMD6 (U(1) << 1) 117 118 #define CMD8_CHECK_PATTERN U(0xAA) 119 #define VHS_2_7_3_6_V BIT(8) 120 121 #define SD_SCR_BUS_WIDTH_1 BIT(8) 122 #define SD_SCR_BUS_WIDTH_4 BIT(10) 123 124 #define SD_SWITCH_FUNC_CHECK 0U 125 #define SD_SWITCH_FUNC_SWITCH BIT(31) 126 #define SD_SWITCH_ALL_GROUPS_MASK GENMASK(23, 0) 127 128 struct mmc_cmd { 129 unsigned int cmd_idx; 130 unsigned int cmd_arg; 131 unsigned int resp_type; 132 unsigned int resp_data[4]; 133 }; 134 135 struct mmc_ops { 136 void (*init)(void); 137 int (*send_cmd)(struct mmc_cmd *cmd); 138 int (*set_ios)(unsigned int clk, unsigned int width); 139 int (*prepare)(int lba, uintptr_t buf, size_t size); 140 int (*read)(int lba, uintptr_t buf, size_t size); 141 int (*write)(int lba, const uintptr_t buf, size_t size); 142 }; 143 144 struct mmc_csd_emmc { 145 unsigned int not_used: 1; 146 unsigned int crc: 7; 147 unsigned int ecc: 2; 148 unsigned int file_format: 2; 149 unsigned int tmp_write_protect: 1; 150 unsigned int perm_write_protect: 1; 151 unsigned int copy: 1; 152 unsigned int file_format_grp: 1; 153 154 unsigned int reserved_1: 5; 155 unsigned int write_bl_partial: 1; 156 unsigned int write_bl_len: 4; 157 unsigned int r2w_factor: 3; 158 unsigned int default_ecc: 2; 159 unsigned int wp_grp_enable: 1; 160 161 unsigned int wp_grp_size: 5; 162 unsigned int erase_grp_mult: 5; 163 unsigned int erase_grp_size: 5; 164 unsigned int c_size_mult: 3; 165 unsigned int vdd_w_curr_max: 3; 166 unsigned int vdd_w_curr_min: 3; 167 unsigned int vdd_r_curr_max: 3; 168 unsigned int vdd_r_curr_min: 3; 169 unsigned int c_size_low: 2; 170 171 unsigned int c_size_high: 10; 172 unsigned int reserved_2: 2; 173 unsigned int dsr_imp: 1; 174 unsigned int read_blk_misalign: 1; 175 unsigned int write_blk_misalign: 1; 176 unsigned int read_bl_partial: 1; 177 unsigned int read_bl_len: 4; 178 unsigned int ccc: 12; 179 180 unsigned int tran_speed: 8; 181 unsigned int nsac: 8; 182 unsigned int taac: 8; 183 unsigned int reserved_3: 2; 184 unsigned int spec_vers: 4; 185 unsigned int csd_structure: 2; 186 }; 187 188 struct mmc_csd_sd_v2 { 189 unsigned int not_used: 1; 190 unsigned int crc: 7; 191 unsigned int reserved_1: 2; 192 unsigned int file_format: 2; 193 unsigned int tmp_write_protect: 1; 194 unsigned int perm_write_protect: 1; 195 unsigned int copy: 1; 196 unsigned int file_format_grp: 1; 197 198 unsigned int reserved_2: 5; 199 unsigned int write_bl_partial: 1; 200 unsigned int write_bl_len: 4; 201 unsigned int r2w_factor: 3; 202 unsigned int reserved_3: 2; 203 unsigned int wp_grp_enable: 1; 204 205 unsigned int wp_grp_size: 7; 206 unsigned int sector_size: 7; 207 unsigned int erase_block_en: 1; 208 unsigned int reserved_4: 1; 209 unsigned int c_size_low: 16; 210 211 unsigned int c_size_high: 6; 212 unsigned int reserved_5: 6; 213 unsigned int dsr_imp: 1; 214 unsigned int read_blk_misalign: 1; 215 unsigned int write_blk_misalign: 1; 216 unsigned int read_bl_partial: 1; 217 unsigned int read_bl_len: 4; 218 unsigned int ccc: 12; 219 220 unsigned int tran_speed: 8; 221 unsigned int nsac: 8; 222 unsigned int taac: 8; 223 unsigned int reserved_6: 6; 224 unsigned int csd_structure: 2; 225 }; 226 227 struct sd_switch_status { 228 unsigned short max_current; 229 unsigned short support_g6; 230 unsigned short support_g5; 231 unsigned short support_g4; 232 unsigned short support_g3; 233 unsigned short support_g2; 234 unsigned short support_g1; 235 unsigned char sel_g6_g5; 236 unsigned char sel_g4_g3; 237 unsigned char sel_g2_g1; 238 unsigned char data_struct_ver; 239 unsigned short busy_g6; 240 unsigned short busy_g5; 241 unsigned short busy_g4; 242 unsigned short busy_g3; 243 unsigned short busy_g2; 244 unsigned short busy_g1; 245 unsigned short reserved[17]; 246 }; 247 248 enum mmc_device_type { 249 MMC_IS_EMMC, 250 MMC_IS_SD, 251 MMC_IS_SD_HC, 252 }; 253 254 struct mmc_device_info { 255 unsigned long long device_size; /* Size of device in bytes */ 256 unsigned int block_size; /* Block size in bytes */ 257 unsigned int max_bus_freq; /* Max bus freq in Hz */ 258 unsigned int ocr_voltage; /* OCR voltage */ 259 enum mmc_device_type mmc_dev_type; /* Type of MMC */ 260 }; 261 262 size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size); 263 size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size); 264 size_t mmc_erase_blocks(int lba, size_t size); 265 int mmc_part_switch_current_boot(void); 266 int mmc_part_switch_user(void); 267 size_t mmc_boot_part_size(void); 268 size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size); 269 int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, 270 unsigned int width, unsigned int flags, 271 struct mmc_device_info *device_info); 272 273 #endif /* MMC_H */ 274