xref: /rk3399_ARM-atf/include/drivers/mmc.h (revision ea315a69de68a664d774c68088b0e4f48b1303e1)
1ad71d45eSYann Gautier /*
2ad71d45eSYann Gautier  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3ad71d45eSYann Gautier  *
4ad71d45eSYann Gautier  * SPDX-License-Identifier: BSD-3-Clause
5ad71d45eSYann Gautier  */
6ad71d45eSYann Gautier 
7ad71d45eSYann Gautier #ifndef __MMC_H__
8ad71d45eSYann Gautier #define __MMC_H__
9ad71d45eSYann Gautier 
10ad71d45eSYann Gautier #include <stdint.h>
11ad71d45eSYann Gautier #include <utils_def.h>
12ad71d45eSYann Gautier 
13ad71d45eSYann Gautier #define MMC_BLOCK_SIZE			U(512)
14ad71d45eSYann Gautier #define MMC_BLOCK_MASK			(MMC_BLOCK_SIZE - U(1))
15ad71d45eSYann Gautier #define MMC_BOOT_CLK_RATE		(400 * 1000)
16ad71d45eSYann Gautier 
17ad71d45eSYann Gautier #define MMC_CMD(_x)			U(_x)
18ad71d45eSYann Gautier 
19ad71d45eSYann Gautier #define MMC_ACMD(_x)			U(_x)
20ad71d45eSYann Gautier 
21ad71d45eSYann Gautier #define OCR_POWERUP			BIT(31)
22ad71d45eSYann Gautier #define OCR_HCS				BIT(30)
23ad71d45eSYann Gautier #define OCR_BYTE_MODE			(U(0) << 29)
24ad71d45eSYann Gautier #define OCR_SECTOR_MODE			(U(2) << 29)
25ad71d45eSYann Gautier #define OCR_ACCESS_MODE_MASK		(U(3) << 29)
26ad71d45eSYann Gautier #define OCR_3_5_3_6			BIT(23)
27ad71d45eSYann Gautier #define OCR_3_4_3_5			BIT(22)
28ad71d45eSYann Gautier #define OCR_3_3_3_4			BIT(21)
29ad71d45eSYann Gautier #define OCR_3_2_3_3			BIT(20)
30ad71d45eSYann Gautier #define OCR_3_1_3_2			BIT(19)
31ad71d45eSYann Gautier #define OCR_3_0_3_1			BIT(18)
32ad71d45eSYann Gautier #define OCR_2_9_3_0			BIT(17)
33ad71d45eSYann Gautier #define OCR_2_8_2_9			BIT(16)
34ad71d45eSYann Gautier #define OCR_2_7_2_8			BIT(15)
35ad71d45eSYann Gautier #define OCR_VDD_MIN_2V7			GENMASK(23, 15)
36ad71d45eSYann Gautier #define OCR_VDD_MIN_2V0			GENMASK(14, 8)
37ad71d45eSYann Gautier #define OCR_VDD_MIN_1V7			BIT(7)
38ad71d45eSYann Gautier 
39ad71d45eSYann Gautier #define MMC_RESPONSE_R(_x)		U(_x)
40ad71d45eSYann Gautier 
41ad71d45eSYann Gautier /* Value randomly chosen for eMMC RCA, it should be > 1 */
42ad71d45eSYann Gautier #define MMC_FIX_RCA			6
43ad71d45eSYann Gautier #define RCA_SHIFT_OFFSET		16
44ad71d45eSYann Gautier 
45ad71d45eSYann Gautier #define CMD_EXTCSD_PARTITION_CONFIG	179
46ad71d45eSYann Gautier #define CMD_EXTCSD_BUS_WIDTH		183
47ad71d45eSYann Gautier #define CMD_EXTCSD_HS_TIMING		185
48ad71d45eSYann Gautier #define CMD_EXTCSD_SEC_CNT		212
49ad71d45eSYann Gautier 
50ad71d45eSYann Gautier #define PART_CFG_BOOT_PARTITION1_ENABLE	(U(1) << 3)
51ad71d45eSYann Gautier #define PART_CFG_PARTITION1_ACCESS	(U(1) << 0)
52ad71d45eSYann Gautier 
53ad71d45eSYann Gautier /* Values in EXT CSD register */
54ad71d45eSYann Gautier #define MMC_BUS_WIDTH_1			U(0)
55ad71d45eSYann Gautier #define MMC_BUS_WIDTH_4			U(1)
56ad71d45eSYann Gautier #define MMC_BUS_WIDTH_8			U(2)
57ad71d45eSYann Gautier #define MMC_BUS_WIDTH_DDR_4		U(5)
58ad71d45eSYann Gautier #define MMC_BUS_WIDTH_DDR_8		U(6)
59ad71d45eSYann Gautier #define MMC_BOOT_MODE_BACKWARD		(U(0) << 3)
60ad71d45eSYann Gautier #define MMC_BOOT_MODE_HS_TIMING		(U(1) << 3)
61ad71d45eSYann Gautier #define MMC_BOOT_MODE_DDR		(U(2) << 3)
62ad71d45eSYann Gautier 
63ad71d45eSYann Gautier #define EXTCSD_SET_CMD			(U(0) << 24)
64ad71d45eSYann Gautier #define EXTCSD_SET_BITS			(U(1) << 24)
65ad71d45eSYann Gautier #define EXTCSD_CLR_BITS			(U(2) << 24)
66ad71d45eSYann Gautier #define EXTCSD_WRITE_BYTES		(U(3) << 24)
67ad71d45eSYann Gautier #define EXTCSD_CMD(x)			(((x) & 0xff) << 16)
68ad71d45eSYann Gautier #define EXTCSD_VALUE(x)			(((x) & 0xff) << 8)
69ad71d45eSYann Gautier #define EXTCSD_CMD_SET_NORMAL		U(1)
70ad71d45eSYann Gautier 
71ad71d45eSYann Gautier #define CSD_TRAN_SPEED_UNIT_MASK	GENMASK(2, 0)
72ad71d45eSYann Gautier #define CSD_TRAN_SPEED_MULT_MASK	GENMASK(6, 3)
73ad71d45eSYann Gautier #define CSD_TRAN_SPEED_MULT_SHIFT	3
74ad71d45eSYann Gautier 
75ad71d45eSYann Gautier #define STATUS_CURRENT_STATE(x)		(((x) & 0xf) << 9)
76ad71d45eSYann Gautier #define STATUS_READY_FOR_DATA		BIT(8)
77ad71d45eSYann Gautier #define STATUS_SWITCH_ERROR		BIT(7)
78ad71d45eSYann Gautier #define MMC_GET_STATE(x)		(((x) >> 9) & 0xf)
79ad71d45eSYann Gautier #define MMC_STATE_IDLE			0
80ad71d45eSYann Gautier #define MMC_STATE_READY			1
81ad71d45eSYann Gautier #define MMC_STATE_IDENT			2
82ad71d45eSYann Gautier #define MMC_STATE_STBY			3
83ad71d45eSYann Gautier #define MMC_STATE_TRAN			4
84ad71d45eSYann Gautier #define MMC_STATE_DATA			5
85ad71d45eSYann Gautier #define MMC_STATE_RCV			6
86ad71d45eSYann Gautier #define MMC_STATE_PRG			7
87ad71d45eSYann Gautier #define MMC_STATE_DIS			8
88ad71d45eSYann Gautier #define MMC_STATE_BTST			9
89ad71d45eSYann Gautier #define MMC_STATE_SLP			10
90ad71d45eSYann Gautier 
91ad71d45eSYann Gautier #define MMC_FLAG_CMD23			(U(1) << 0)
92ad71d45eSYann Gautier 
93ad71d45eSYann Gautier #define CMD8_CHECK_PATTERN		U(0xAA)
94ad71d45eSYann Gautier #define VHS_2_7_3_6_V			BIT(8)
95ad71d45eSYann Gautier 
96ad71d45eSYann Gautier #define SD_SCR_BUS_WIDTH_1		BIT(8)
97ad71d45eSYann Gautier #define SD_SCR_BUS_WIDTH_4		BIT(10)
98ad71d45eSYann Gautier 
99ad71d45eSYann Gautier struct mmc_cmd {
100ad71d45eSYann Gautier 	unsigned int	cmd_idx;
101ad71d45eSYann Gautier 	unsigned int	cmd_arg;
102ad71d45eSYann Gautier 	unsigned int	resp_type;
103ad71d45eSYann Gautier 	unsigned int	resp_data[4];
104ad71d45eSYann Gautier };
105ad71d45eSYann Gautier 
106ad71d45eSYann Gautier struct mmc_ops {
107ad71d45eSYann Gautier 	void (*init)(void);
108ad71d45eSYann Gautier 	int (*send_cmd)(struct mmc_cmd *cmd);
109ad71d45eSYann Gautier 	int (*set_ios)(unsigned int clk, unsigned int width);
110ad71d45eSYann Gautier 	int (*prepare)(int lba, uintptr_t buf, size_t size);
111ad71d45eSYann Gautier 	int (*read)(int lba, uintptr_t buf, size_t size);
112ad71d45eSYann Gautier 	int (*write)(int lba, const uintptr_t buf, size_t size);
113ad71d45eSYann Gautier };
114ad71d45eSYann Gautier 
115ad71d45eSYann Gautier struct mmc_csd_emmc {
116ad71d45eSYann Gautier 	unsigned int		not_used:		1;
117ad71d45eSYann Gautier 	unsigned int		crc:			7;
118ad71d45eSYann Gautier 	unsigned int		ecc:			2;
119ad71d45eSYann Gautier 	unsigned int		file_format:		2;
120ad71d45eSYann Gautier 	unsigned int		tmp_write_protect:	1;
121ad71d45eSYann Gautier 	unsigned int		perm_write_protect:	1;
122ad71d45eSYann Gautier 	unsigned int		copy:			1;
123ad71d45eSYann Gautier 	unsigned int		file_format_grp:	1;
124ad71d45eSYann Gautier 
125ad71d45eSYann Gautier 	unsigned int		reserved_1:		5;
126ad71d45eSYann Gautier 	unsigned int		write_bl_partial:	1;
127ad71d45eSYann Gautier 	unsigned int		write_bl_len:		4;
128ad71d45eSYann Gautier 	unsigned int		r2w_factor:		3;
129ad71d45eSYann Gautier 	unsigned int		default_ecc:		2;
130ad71d45eSYann Gautier 	unsigned int		wp_grp_enable:		1;
131ad71d45eSYann Gautier 
132ad71d45eSYann Gautier 	unsigned int		wp_grp_size:		5;
133ad71d45eSYann Gautier 	unsigned int		erase_grp_mult:		5;
134ad71d45eSYann Gautier 	unsigned int		erase_grp_size:		5;
135ad71d45eSYann Gautier 	unsigned int		c_size_mult:		3;
136ad71d45eSYann Gautier 	unsigned int		vdd_w_curr_max:		3;
137ad71d45eSYann Gautier 	unsigned int		vdd_w_curr_min:		3;
138ad71d45eSYann Gautier 	unsigned int		vdd_r_curr_max:		3;
139ad71d45eSYann Gautier 	unsigned int		vdd_r_curr_min:		3;
140ad71d45eSYann Gautier 	unsigned int		c_size_low:		2;
141ad71d45eSYann Gautier 
142ad71d45eSYann Gautier 	unsigned int		c_size_high:		10;
143ad71d45eSYann Gautier 	unsigned int		reserved_2:		2;
144ad71d45eSYann Gautier 	unsigned int		dsr_imp:		1;
145ad71d45eSYann Gautier 	unsigned int		read_blk_misalign:	1;
146ad71d45eSYann Gautier 	unsigned int		write_blk_misalign:	1;
147ad71d45eSYann Gautier 	unsigned int		read_bl_partial:	1;
148ad71d45eSYann Gautier 	unsigned int		read_bl_len:		4;
149ad71d45eSYann Gautier 	unsigned int		ccc:			12;
150ad71d45eSYann Gautier 
151ad71d45eSYann Gautier 	unsigned int		tran_speed:		8;
152ad71d45eSYann Gautier 	unsigned int		nsac:			8;
153ad71d45eSYann Gautier 	unsigned int		taac:			8;
154ad71d45eSYann Gautier 	unsigned int		reserved_3:		2;
155ad71d45eSYann Gautier 	unsigned int		spec_vers:		4;
156ad71d45eSYann Gautier 	unsigned int		csd_structure:		2;
157ad71d45eSYann Gautier };
158ad71d45eSYann Gautier 
159ad71d45eSYann Gautier struct mmc_csd_sd_v2 {
160ad71d45eSYann Gautier 	unsigned int		not_used:		1;
161ad71d45eSYann Gautier 	unsigned int		crc:			7;
162ad71d45eSYann Gautier 	unsigned int		reserved_1:		2;
163ad71d45eSYann Gautier 	unsigned int		file_format:		2;
164ad71d45eSYann Gautier 	unsigned int		tmp_write_protect:	1;
165ad71d45eSYann Gautier 	unsigned int		perm_write_protect:	1;
166ad71d45eSYann Gautier 	unsigned int		copy:			1;
167ad71d45eSYann Gautier 	unsigned int		file_format_grp:	1;
168ad71d45eSYann Gautier 
169ad71d45eSYann Gautier 	unsigned int		reserved_2:		5;
170ad71d45eSYann Gautier 	unsigned int		write_bl_partial:	1;
171ad71d45eSYann Gautier 	unsigned int		write_bl_len:		4;
172ad71d45eSYann Gautier 	unsigned int		r2w_factor:		3;
173ad71d45eSYann Gautier 	unsigned int		reserved_3:		2;
174ad71d45eSYann Gautier 	unsigned int		wp_grp_enable:		1;
175ad71d45eSYann Gautier 
176ad71d45eSYann Gautier 	unsigned int		wp_grp_size:		7;
177ad71d45eSYann Gautier 	unsigned int		sector_size:		7;
178ad71d45eSYann Gautier 	unsigned int		erase_block_en:		1;
179ad71d45eSYann Gautier 	unsigned int		reserved_4:		1;
180ad71d45eSYann Gautier 	unsigned int		c_size_low:		16;
181ad71d45eSYann Gautier 
182ad71d45eSYann Gautier 	unsigned int		c_size_high:		6;
183ad71d45eSYann Gautier 	unsigned int		reserved_5:		6;
184ad71d45eSYann Gautier 	unsigned int		dsr_imp:		1;
185ad71d45eSYann Gautier 	unsigned int		read_blk_misalign:	1;
186ad71d45eSYann Gautier 	unsigned int		write_blk_misalign:	1;
187ad71d45eSYann Gautier 	unsigned int		read_bl_partial:	1;
188ad71d45eSYann Gautier 	unsigned int		read_bl_len:		4;
189ad71d45eSYann Gautier 	unsigned int		ccc:			12;
190ad71d45eSYann Gautier 
191ad71d45eSYann Gautier 	unsigned int		tran_speed:		8;
192ad71d45eSYann Gautier 	unsigned int		nsac:			8;
193ad71d45eSYann Gautier 	unsigned int		taac:			8;
194ad71d45eSYann Gautier 	unsigned int		reserved_6:		6;
195ad71d45eSYann Gautier 	unsigned int		csd_structure:		2;
196ad71d45eSYann Gautier };
197ad71d45eSYann Gautier 
198ad71d45eSYann Gautier enum mmc_device_type {
199ad71d45eSYann Gautier 	MMC_IS_EMMC,
200ad71d45eSYann Gautier 	MMC_IS_SD,
201ad71d45eSYann Gautier 	MMC_IS_SD_HC,
202ad71d45eSYann Gautier };
203ad71d45eSYann Gautier 
204ad71d45eSYann Gautier struct mmc_device_info {
205ad71d45eSYann Gautier 	unsigned long long	device_size;	/* Size of device in bytes */
206ad71d45eSYann Gautier 	unsigned int		block_size;	/* Block size in bytes */
207ad71d45eSYann Gautier 	unsigned int		max_bus_freq;	/* Max bus freq in Hz */
208ad71d45eSYann Gautier 	enum mmc_device_type	mmc_dev_type;	/* Type of MMC */
209ad71d45eSYann Gautier };
210ad71d45eSYann Gautier 
211*ea315a69SHaojian Zhuang size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
212*ea315a69SHaojian Zhuang size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
213*ea315a69SHaojian Zhuang size_t mmc_erase_blocks(int lba, size_t size);
214*ea315a69SHaojian Zhuang size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
215*ea315a69SHaojian Zhuang size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
216*ea315a69SHaojian Zhuang size_t mmc_rpmb_erase_blocks(int lba, size_t size);
217ad71d45eSYann Gautier int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
218ad71d45eSYann Gautier 	     unsigned int width, unsigned int flags,
219ad71d45eSYann Gautier 	     struct mmc_device_info *device_info);
220ad71d45eSYann Gautier 
221ad71d45eSYann Gautier #endif	/* __MMC_H__ */
222