1*ad71d45eSYann Gautier /* 2*ad71d45eSYann Gautier * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*ad71d45eSYann Gautier * 4*ad71d45eSYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*ad71d45eSYann Gautier */ 6*ad71d45eSYann Gautier 7*ad71d45eSYann Gautier #ifndef __MMC_H__ 8*ad71d45eSYann Gautier #define __MMC_H__ 9*ad71d45eSYann Gautier 10*ad71d45eSYann Gautier #include <stdint.h> 11*ad71d45eSYann Gautier #include <utils_def.h> 12*ad71d45eSYann Gautier 13*ad71d45eSYann Gautier #define MMC_BLOCK_SIZE U(512) 14*ad71d45eSYann Gautier #define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1)) 15*ad71d45eSYann Gautier #define MMC_BOOT_CLK_RATE (400 * 1000) 16*ad71d45eSYann Gautier 17*ad71d45eSYann Gautier #define MMC_CMD(_x) U(_x) 18*ad71d45eSYann Gautier 19*ad71d45eSYann Gautier #define MMC_ACMD(_x) U(_x) 20*ad71d45eSYann Gautier 21*ad71d45eSYann Gautier #define OCR_POWERUP BIT(31) 22*ad71d45eSYann Gautier #define OCR_HCS BIT(30) 23*ad71d45eSYann Gautier #define OCR_BYTE_MODE (U(0) << 29) 24*ad71d45eSYann Gautier #define OCR_SECTOR_MODE (U(2) << 29) 25*ad71d45eSYann Gautier #define OCR_ACCESS_MODE_MASK (U(3) << 29) 26*ad71d45eSYann Gautier #define OCR_3_5_3_6 BIT(23) 27*ad71d45eSYann Gautier #define OCR_3_4_3_5 BIT(22) 28*ad71d45eSYann Gautier #define OCR_3_3_3_4 BIT(21) 29*ad71d45eSYann Gautier #define OCR_3_2_3_3 BIT(20) 30*ad71d45eSYann Gautier #define OCR_3_1_3_2 BIT(19) 31*ad71d45eSYann Gautier #define OCR_3_0_3_1 BIT(18) 32*ad71d45eSYann Gautier #define OCR_2_9_3_0 BIT(17) 33*ad71d45eSYann Gautier #define OCR_2_8_2_9 BIT(16) 34*ad71d45eSYann Gautier #define OCR_2_7_2_8 BIT(15) 35*ad71d45eSYann Gautier #define OCR_VDD_MIN_2V7 GENMASK(23, 15) 36*ad71d45eSYann Gautier #define OCR_VDD_MIN_2V0 GENMASK(14, 8) 37*ad71d45eSYann Gautier #define OCR_VDD_MIN_1V7 BIT(7) 38*ad71d45eSYann Gautier 39*ad71d45eSYann Gautier #define MMC_RESPONSE_R(_x) U(_x) 40*ad71d45eSYann Gautier 41*ad71d45eSYann Gautier /* Value randomly chosen for eMMC RCA, it should be > 1 */ 42*ad71d45eSYann Gautier #define MMC_FIX_RCA 6 43*ad71d45eSYann Gautier #define RCA_SHIFT_OFFSET 16 44*ad71d45eSYann Gautier 45*ad71d45eSYann Gautier #define CMD_EXTCSD_PARTITION_CONFIG 179 46*ad71d45eSYann Gautier #define CMD_EXTCSD_BUS_WIDTH 183 47*ad71d45eSYann Gautier #define CMD_EXTCSD_HS_TIMING 185 48*ad71d45eSYann Gautier #define CMD_EXTCSD_SEC_CNT 212 49*ad71d45eSYann Gautier 50*ad71d45eSYann Gautier #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) 51*ad71d45eSYann Gautier #define PART_CFG_PARTITION1_ACCESS (U(1) << 0) 52*ad71d45eSYann Gautier 53*ad71d45eSYann Gautier /* Values in EXT CSD register */ 54*ad71d45eSYann Gautier #define MMC_BUS_WIDTH_1 U(0) 55*ad71d45eSYann Gautier #define MMC_BUS_WIDTH_4 U(1) 56*ad71d45eSYann Gautier #define MMC_BUS_WIDTH_8 U(2) 57*ad71d45eSYann Gautier #define MMC_BUS_WIDTH_DDR_4 U(5) 58*ad71d45eSYann Gautier #define MMC_BUS_WIDTH_DDR_8 U(6) 59*ad71d45eSYann Gautier #define MMC_BOOT_MODE_BACKWARD (U(0) << 3) 60*ad71d45eSYann Gautier #define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) 61*ad71d45eSYann Gautier #define MMC_BOOT_MODE_DDR (U(2) << 3) 62*ad71d45eSYann Gautier 63*ad71d45eSYann Gautier #define EXTCSD_SET_CMD (U(0) << 24) 64*ad71d45eSYann Gautier #define EXTCSD_SET_BITS (U(1) << 24) 65*ad71d45eSYann Gautier #define EXTCSD_CLR_BITS (U(2) << 24) 66*ad71d45eSYann Gautier #define EXTCSD_WRITE_BYTES (U(3) << 24) 67*ad71d45eSYann Gautier #define EXTCSD_CMD(x) (((x) & 0xff) << 16) 68*ad71d45eSYann Gautier #define EXTCSD_VALUE(x) (((x) & 0xff) << 8) 69*ad71d45eSYann Gautier #define EXTCSD_CMD_SET_NORMAL U(1) 70*ad71d45eSYann Gautier 71*ad71d45eSYann Gautier #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) 72*ad71d45eSYann Gautier #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) 73*ad71d45eSYann Gautier #define CSD_TRAN_SPEED_MULT_SHIFT 3 74*ad71d45eSYann Gautier 75*ad71d45eSYann Gautier #define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) 76*ad71d45eSYann Gautier #define STATUS_READY_FOR_DATA BIT(8) 77*ad71d45eSYann Gautier #define STATUS_SWITCH_ERROR BIT(7) 78*ad71d45eSYann Gautier #define MMC_GET_STATE(x) (((x) >> 9) & 0xf) 79*ad71d45eSYann Gautier #define MMC_STATE_IDLE 0 80*ad71d45eSYann Gautier #define MMC_STATE_READY 1 81*ad71d45eSYann Gautier #define MMC_STATE_IDENT 2 82*ad71d45eSYann Gautier #define MMC_STATE_STBY 3 83*ad71d45eSYann Gautier #define MMC_STATE_TRAN 4 84*ad71d45eSYann Gautier #define MMC_STATE_DATA 5 85*ad71d45eSYann Gautier #define MMC_STATE_RCV 6 86*ad71d45eSYann Gautier #define MMC_STATE_PRG 7 87*ad71d45eSYann Gautier #define MMC_STATE_DIS 8 88*ad71d45eSYann Gautier #define MMC_STATE_BTST 9 89*ad71d45eSYann Gautier #define MMC_STATE_SLP 10 90*ad71d45eSYann Gautier 91*ad71d45eSYann Gautier #define MMC_FLAG_CMD23 (U(1) << 0) 92*ad71d45eSYann Gautier 93*ad71d45eSYann Gautier #define CMD8_CHECK_PATTERN U(0xAA) 94*ad71d45eSYann Gautier #define VHS_2_7_3_6_V BIT(8) 95*ad71d45eSYann Gautier 96*ad71d45eSYann Gautier #define SD_SCR_BUS_WIDTH_1 BIT(8) 97*ad71d45eSYann Gautier #define SD_SCR_BUS_WIDTH_4 BIT(10) 98*ad71d45eSYann Gautier 99*ad71d45eSYann Gautier struct mmc_cmd { 100*ad71d45eSYann Gautier unsigned int cmd_idx; 101*ad71d45eSYann Gautier unsigned int cmd_arg; 102*ad71d45eSYann Gautier unsigned int resp_type; 103*ad71d45eSYann Gautier unsigned int resp_data[4]; 104*ad71d45eSYann Gautier }; 105*ad71d45eSYann Gautier 106*ad71d45eSYann Gautier struct mmc_ops { 107*ad71d45eSYann Gautier void (*init)(void); 108*ad71d45eSYann Gautier int (*send_cmd)(struct mmc_cmd *cmd); 109*ad71d45eSYann Gautier int (*set_ios)(unsigned int clk, unsigned int width); 110*ad71d45eSYann Gautier int (*prepare)(int lba, uintptr_t buf, size_t size); 111*ad71d45eSYann Gautier int (*read)(int lba, uintptr_t buf, size_t size); 112*ad71d45eSYann Gautier int (*write)(int lba, const uintptr_t buf, size_t size); 113*ad71d45eSYann Gautier }; 114*ad71d45eSYann Gautier 115*ad71d45eSYann Gautier struct mmc_csd_emmc { 116*ad71d45eSYann Gautier unsigned int not_used: 1; 117*ad71d45eSYann Gautier unsigned int crc: 7; 118*ad71d45eSYann Gautier unsigned int ecc: 2; 119*ad71d45eSYann Gautier unsigned int file_format: 2; 120*ad71d45eSYann Gautier unsigned int tmp_write_protect: 1; 121*ad71d45eSYann Gautier unsigned int perm_write_protect: 1; 122*ad71d45eSYann Gautier unsigned int copy: 1; 123*ad71d45eSYann Gautier unsigned int file_format_grp: 1; 124*ad71d45eSYann Gautier 125*ad71d45eSYann Gautier unsigned int reserved_1: 5; 126*ad71d45eSYann Gautier unsigned int write_bl_partial: 1; 127*ad71d45eSYann Gautier unsigned int write_bl_len: 4; 128*ad71d45eSYann Gautier unsigned int r2w_factor: 3; 129*ad71d45eSYann Gautier unsigned int default_ecc: 2; 130*ad71d45eSYann Gautier unsigned int wp_grp_enable: 1; 131*ad71d45eSYann Gautier 132*ad71d45eSYann Gautier unsigned int wp_grp_size: 5; 133*ad71d45eSYann Gautier unsigned int erase_grp_mult: 5; 134*ad71d45eSYann Gautier unsigned int erase_grp_size: 5; 135*ad71d45eSYann Gautier unsigned int c_size_mult: 3; 136*ad71d45eSYann Gautier unsigned int vdd_w_curr_max: 3; 137*ad71d45eSYann Gautier unsigned int vdd_w_curr_min: 3; 138*ad71d45eSYann Gautier unsigned int vdd_r_curr_max: 3; 139*ad71d45eSYann Gautier unsigned int vdd_r_curr_min: 3; 140*ad71d45eSYann Gautier unsigned int c_size_low: 2; 141*ad71d45eSYann Gautier 142*ad71d45eSYann Gautier unsigned int c_size_high: 10; 143*ad71d45eSYann Gautier unsigned int reserved_2: 2; 144*ad71d45eSYann Gautier unsigned int dsr_imp: 1; 145*ad71d45eSYann Gautier unsigned int read_blk_misalign: 1; 146*ad71d45eSYann Gautier unsigned int write_blk_misalign: 1; 147*ad71d45eSYann Gautier unsigned int read_bl_partial: 1; 148*ad71d45eSYann Gautier unsigned int read_bl_len: 4; 149*ad71d45eSYann Gautier unsigned int ccc: 12; 150*ad71d45eSYann Gautier 151*ad71d45eSYann Gautier unsigned int tran_speed: 8; 152*ad71d45eSYann Gautier unsigned int nsac: 8; 153*ad71d45eSYann Gautier unsigned int taac: 8; 154*ad71d45eSYann Gautier unsigned int reserved_3: 2; 155*ad71d45eSYann Gautier unsigned int spec_vers: 4; 156*ad71d45eSYann Gautier unsigned int csd_structure: 2; 157*ad71d45eSYann Gautier }; 158*ad71d45eSYann Gautier 159*ad71d45eSYann Gautier struct mmc_csd_sd_v2 { 160*ad71d45eSYann Gautier unsigned int not_used: 1; 161*ad71d45eSYann Gautier unsigned int crc: 7; 162*ad71d45eSYann Gautier unsigned int reserved_1: 2; 163*ad71d45eSYann Gautier unsigned int file_format: 2; 164*ad71d45eSYann Gautier unsigned int tmp_write_protect: 1; 165*ad71d45eSYann Gautier unsigned int perm_write_protect: 1; 166*ad71d45eSYann Gautier unsigned int copy: 1; 167*ad71d45eSYann Gautier unsigned int file_format_grp: 1; 168*ad71d45eSYann Gautier 169*ad71d45eSYann Gautier unsigned int reserved_2: 5; 170*ad71d45eSYann Gautier unsigned int write_bl_partial: 1; 171*ad71d45eSYann Gautier unsigned int write_bl_len: 4; 172*ad71d45eSYann Gautier unsigned int r2w_factor: 3; 173*ad71d45eSYann Gautier unsigned int reserved_3: 2; 174*ad71d45eSYann Gautier unsigned int wp_grp_enable: 1; 175*ad71d45eSYann Gautier 176*ad71d45eSYann Gautier unsigned int wp_grp_size: 7; 177*ad71d45eSYann Gautier unsigned int sector_size: 7; 178*ad71d45eSYann Gautier unsigned int erase_block_en: 1; 179*ad71d45eSYann Gautier unsigned int reserved_4: 1; 180*ad71d45eSYann Gautier unsigned int c_size_low: 16; 181*ad71d45eSYann Gautier 182*ad71d45eSYann Gautier unsigned int c_size_high: 6; 183*ad71d45eSYann Gautier unsigned int reserved_5: 6; 184*ad71d45eSYann Gautier unsigned int dsr_imp: 1; 185*ad71d45eSYann Gautier unsigned int read_blk_misalign: 1; 186*ad71d45eSYann Gautier unsigned int write_blk_misalign: 1; 187*ad71d45eSYann Gautier unsigned int read_bl_partial: 1; 188*ad71d45eSYann Gautier unsigned int read_bl_len: 4; 189*ad71d45eSYann Gautier unsigned int ccc: 12; 190*ad71d45eSYann Gautier 191*ad71d45eSYann Gautier unsigned int tran_speed: 8; 192*ad71d45eSYann Gautier unsigned int nsac: 8; 193*ad71d45eSYann Gautier unsigned int taac: 8; 194*ad71d45eSYann Gautier unsigned int reserved_6: 6; 195*ad71d45eSYann Gautier unsigned int csd_structure: 2; 196*ad71d45eSYann Gautier }; 197*ad71d45eSYann Gautier 198*ad71d45eSYann Gautier enum mmc_device_type { 199*ad71d45eSYann Gautier MMC_IS_EMMC, 200*ad71d45eSYann Gautier MMC_IS_SD, 201*ad71d45eSYann Gautier MMC_IS_SD_HC, 202*ad71d45eSYann Gautier }; 203*ad71d45eSYann Gautier 204*ad71d45eSYann Gautier struct mmc_device_info { 205*ad71d45eSYann Gautier unsigned long long device_size; /* Size of device in bytes */ 206*ad71d45eSYann Gautier unsigned int block_size; /* Block size in bytes */ 207*ad71d45eSYann Gautier unsigned int max_bus_freq; /* Max bus freq in Hz */ 208*ad71d45eSYann Gautier enum mmc_device_type mmc_dev_type; /* Type of MMC */ 209*ad71d45eSYann Gautier }; 210*ad71d45eSYann Gautier 211*ad71d45eSYann Gautier size_t mmc_read_blocks(unsigned int lba, uintptr_t buf, size_t size); 212*ad71d45eSYann Gautier size_t mmc_write_blocks(unsigned int lba, const uintptr_t buf, size_t size); 213*ad71d45eSYann Gautier size_t mmc_erase_blocks(unsigned int lba, size_t size); 214*ad71d45eSYann Gautier size_t mmc_rpmb_read_blocks(unsigned int lba, uintptr_t buf, size_t size); 215*ad71d45eSYann Gautier size_t mmc_rpmb_write_blocks(unsigned int lba, const uintptr_t buf, 216*ad71d45eSYann Gautier size_t size); 217*ad71d45eSYann Gautier size_t mmc_rpmb_erase_blocks(unsigned int lba, size_t size); 218*ad71d45eSYann Gautier int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, 219*ad71d45eSYann Gautier unsigned int width, unsigned int flags, 220*ad71d45eSYann Gautier struct mmc_device_info *device_info); 221*ad71d45eSYann Gautier 222*ad71d45eSYann Gautier #endif /* __MMC_H__ */ 223