1*d7c4420cSKonstantin Porotchkin /* 2*d7c4420cSKonstantin Porotchkin * Copyright (C) 2016 Marvell International Ltd. 3*d7c4420cSKonstantin Porotchkin * 4*d7c4420cSKonstantin Porotchkin * SPDX-License-Identifier: BSD-3-Clause 5*d7c4420cSKonstantin Porotchkin * https://spdx.org/licenses 6*d7c4420cSKonstantin Porotchkin */ 7*d7c4420cSKonstantin Porotchkin 8*d7c4420cSKonstantin Porotchkin #ifndef A3700_CONSOLE_H 9*d7c4420cSKonstantin Porotchkin #define A3700_CONSOLE_H 10*d7c4420cSKonstantin Porotchkin 11*d7c4420cSKonstantin Porotchkin #include <console.h> 12*d7c4420cSKonstantin Porotchkin 13*d7c4420cSKonstantin Porotchkin /* MVEBU UART Registers */ 14*d7c4420cSKonstantin Porotchkin #define UART_RX_REG 0x00 15*d7c4420cSKonstantin Porotchkin #define UART_TX_REG 0x04 16*d7c4420cSKonstantin Porotchkin #define UART_CTRL_REG 0x08 17*d7c4420cSKonstantin Porotchkin #define UART_STATUS_REG 0x0c 18*d7c4420cSKonstantin Porotchkin #define UART_BAUD_REG 0x10 19*d7c4420cSKonstantin Porotchkin #define UART_POSSR_REG 0x14 20*d7c4420cSKonstantin Porotchkin 21*d7c4420cSKonstantin Porotchkin /* FIFO Control Register bits */ 22*d7c4420cSKonstantin Porotchkin #define UARTFCR_FIFOMD_16450 (0 << 6) 23*d7c4420cSKonstantin Porotchkin #define UARTFCR_FIFOMD_16550 (1 << 6) 24*d7c4420cSKonstantin Porotchkin #define UARTFCR_RXTRIG_1 (0 << 6) 25*d7c4420cSKonstantin Porotchkin #define UARTFCR_RXTRIG_4 (1 << 6) 26*d7c4420cSKonstantin Porotchkin #define UARTFCR_RXTRIG_8 (2 << 6) 27*d7c4420cSKonstantin Porotchkin #define UARTFCR_RXTRIG_16 (3 << 6) 28*d7c4420cSKonstantin Porotchkin #define UARTFCR_TXTRIG_1 (0 << 4) 29*d7c4420cSKonstantin Porotchkin #define UARTFCR_TXTRIG_4 (1 << 4) 30*d7c4420cSKonstantin Porotchkin #define UARTFCR_TXTRIG_8 (2 << 4) 31*d7c4420cSKonstantin Porotchkin #define UARTFCR_TXTRIG_16 (3 << 4) 32*d7c4420cSKonstantin Porotchkin #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ 33*d7c4420cSKonstantin Porotchkin #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ 34*d7c4420cSKonstantin Porotchkin #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ 35*d7c4420cSKonstantin Porotchkin #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ 36*d7c4420cSKonstantin Porotchkin 37*d7c4420cSKonstantin Porotchkin /* Line Control Register bits */ 38*d7c4420cSKonstantin Porotchkin #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ 39*d7c4420cSKonstantin Porotchkin #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ 40*d7c4420cSKonstantin Porotchkin #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ 41*d7c4420cSKonstantin Porotchkin #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ 42*d7c4420cSKonstantin Porotchkin #define UARTLCR_PAR (1 << 3) /* Parity */ 43*d7c4420cSKonstantin Porotchkin #define UARTLCR_STOP (1 << 2) /* Stop Bit */ 44*d7c4420cSKonstantin Porotchkin #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ 45*d7c4420cSKonstantin Porotchkin #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ 46*d7c4420cSKonstantin Porotchkin #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ 47*d7c4420cSKonstantin Porotchkin #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ 48*d7c4420cSKonstantin Porotchkin 49*d7c4420cSKonstantin Porotchkin /* Line Status Register bits */ 50*d7c4420cSKonstantin Porotchkin #define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */ 51*d7c4420cSKonstantin Porotchkin 52*d7c4420cSKonstantin Porotchkin /* UART Control Register bits */ 53*d7c4420cSKonstantin Porotchkin #define UART_CTRL_RXFIFO_RESET (1 << 14) 54*d7c4420cSKonstantin Porotchkin #define UART_CTRL_TXFIFO_RESET (1 << 15) 55*d7c4420cSKonstantin Porotchkin #define UARTLSR_TXFIFOEMPTY (1 << 6) 56*d7c4420cSKonstantin Porotchkin 57*d7c4420cSKonstantin Porotchkin #define CONSOLE_T_A3700_BASE CONSOLE_T_DRVDATA 58*d7c4420cSKonstantin Porotchkin 59*d7c4420cSKonstantin Porotchkin #ifndef __ASSEMBLY__ 60*d7c4420cSKonstantin Porotchkin 61*d7c4420cSKonstantin Porotchkin #include <stdint.h> 62*d7c4420cSKonstantin Porotchkin 63*d7c4420cSKonstantin Porotchkin typedef struct { 64*d7c4420cSKonstantin Porotchkin console_t console; 65*d7c4420cSKonstantin Porotchkin uintptr_t base; 66*d7c4420cSKonstantin Porotchkin } console_a3700_t; 67*d7c4420cSKonstantin Porotchkin 68*d7c4420cSKonstantin Porotchkin /* 69*d7c4420cSKonstantin Porotchkin * Initialize a new a3700 console instance and register it with the console 70*d7c4420cSKonstantin Porotchkin * framework. The |console| pointer must point to storage that will be valid 71*d7c4420cSKonstantin Porotchkin * for the lifetime of the console, such as a global or static local variable. 72*d7c4420cSKonstantin Porotchkin * Its contents will be reinitialized from scratch. 73*d7c4420cSKonstantin Porotchkin */ 74*d7c4420cSKonstantin Porotchkin int console_a3700_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, 75*d7c4420cSKonstantin Porotchkin console_a3700_t *console); 76*d7c4420cSKonstantin Porotchkin 77*d7c4420cSKonstantin Porotchkin #endif /*__ASSEMBLY__*/ 78*d7c4420cSKonstantin Porotchkin 79*d7c4420cSKonstantin Porotchkin #endif /* A3700_CONSOLE_H */ 80