xref: /rk3399_ARM-atf/include/drivers/marvell/mochi/cp110_setup.h (revision c42d5eeaf1be694a759a647994efc5ce0eea6a98)
1031542fcSKonstantin Porotchkin /*
2031542fcSKonstantin Porotchkin  * Copyright (C) 2018 Marvell International Ltd.
3031542fcSKonstantin Porotchkin  *
4031542fcSKonstantin Porotchkin  * SPDX-License-Identifier:     BSD-3-Clause
5031542fcSKonstantin Porotchkin  * https://spdx.org/licenses
6031542fcSKonstantin Porotchkin  */
7031542fcSKonstantin Porotchkin 
8031542fcSKonstantin Porotchkin /* CP110 Marvell SoC driver */
9031542fcSKonstantin Porotchkin 
10c3cf06f1SAntonio Nino Diaz #ifndef CP110_SETUP_H
11c3cf06f1SAntonio Nino Diaz #define CP110_SETUP_H
12031542fcSKonstantin Porotchkin 
1309d40e0eSAntonio Nino Diaz #include <lib/mmio.h>
1409d40e0eSAntonio Nino Diaz 
15031542fcSKonstantin Porotchkin #include <mvebu_def.h>
16031542fcSKonstantin Porotchkin 
17031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_ID_REG		(MVEBU_CP_DFX_OFFSET + 0x40)
18031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_ID_OFFSET		(0)
19031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_ID_MASK		(0xffff << MVEBU_DEVICE_ID_OFFSET)
20031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_REV_OFFSET		(16)
21031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_REV_MASK		(0xf << MVEBU_DEVICE_REV_OFFSET)
22031542fcSKonstantin Porotchkin #define MVEBU_70X0_DEV_ID		(0x7040)
23031542fcSKonstantin Porotchkin #define MVEBU_70X0_CP115_DEV_ID		(0x7045)
241ab4df76SChristine Gharzuzi #define MVEBU_3900_DEV_ID		(0x6025)
25031542fcSKonstantin Porotchkin #define MVEBU_80X0_DEV_ID		(0x8040)
26031542fcSKonstantin Porotchkin #define MVEBU_80X0_CP115_DEV_ID		(0x8045)
275bc3643eSBen Peled #define MVEBU_CN9130_DEV_ID		(0x7025)
28031542fcSKonstantin Porotchkin #define MVEBU_CP110_SA_DEV_ID		(0x110)
29031542fcSKonstantin Porotchkin #define MVEBU_CP110_REF_ID_A1		1
30031542fcSKonstantin Porotchkin #define MVEBU_CP110_REF_ID_A2		2
31031542fcSKonstantin Porotchkin #define MAX_STREAM_ID_PER_CP		(0x10)
32031542fcSKonstantin Porotchkin #define STREAM_ID_BASE			(0x40)
33031542fcSKonstantin Porotchkin 
34*c42d5eeaSKonstantin Porotchkin #define MVEBU_SECUREBOOT_CTRL_REG	(MVEBU_RFU_BASE + 0x4730)
35*c42d5eeaSKonstantin Porotchkin #define MVEBU_SECUREBOOT_EN_MASK	BIT(0)
36*c42d5eeaSKonstantin Porotchkin 
37031542fcSKonstantin Porotchkin static inline uint32_t cp110_device_id_get(uintptr_t base)
38031542fcSKonstantin Porotchkin {
39031542fcSKonstantin Porotchkin 	/* Returns:
40031542fcSKonstantin Porotchkin 	 * - MVEBU_70X0_DEV_ID for A70X0 family
41031542fcSKonstantin Porotchkin 	 * - MVEBU_80X0_DEV_ID for A80X0 family
42031542fcSKonstantin Porotchkin 	 * - MVEBU_CP110_SA_DEV_ID for CP that connected stand alone
43031542fcSKonstantin Porotchkin 	 */
44031542fcSKonstantin Porotchkin 	return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) >>
45031542fcSKonstantin Porotchkin 		MVEBU_DEVICE_ID_OFFSET) &
46031542fcSKonstantin Porotchkin 		MVEBU_DEVICE_ID_MASK;
47031542fcSKonstantin Porotchkin }
48031542fcSKonstantin Porotchkin 
49031542fcSKonstantin Porotchkin static inline uint32_t cp110_rev_id_get(uintptr_t base)
50031542fcSKonstantin Porotchkin {
51031542fcSKonstantin Porotchkin 	return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) &
52031542fcSKonstantin Porotchkin 		MVEBU_DEVICE_REV_MASK) >>
53031542fcSKonstantin Porotchkin 		MVEBU_DEVICE_REV_OFFSET;
54031542fcSKonstantin Porotchkin }
55031542fcSKonstantin Porotchkin 
56*c42d5eeaSKonstantin Porotchkin static inline uint32_t is_secure(void)
57*c42d5eeaSKonstantin Porotchkin {
58*c42d5eeaSKonstantin Porotchkin 	return !!(mmio_read_32(MVEBU_SECUREBOOT_CTRL_REG) &
59*c42d5eeaSKonstantin Porotchkin 			       MVEBU_SECUREBOOT_EN_MASK);
60*c42d5eeaSKonstantin Porotchkin }
61*c42d5eeaSKonstantin Porotchkin 
62031542fcSKonstantin Porotchkin void cp110_init(uintptr_t cp110_base, uint32_t stream_id);
63031542fcSKonstantin Porotchkin void cp110_ble_init(uintptr_t cp110_base);
6481646055SGrzegorz Jaszczyk void cp110_amb_init(uintptr_t base);
65031542fcSKonstantin Porotchkin 
66c3cf06f1SAntonio Nino Diaz #endif /* CP110_SETUP_H */
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