1*031542fcSKonstantin Porotchkin /* 2*031542fcSKonstantin Porotchkin * Copyright (C) 2018 Marvell International Ltd. 3*031542fcSKonstantin Porotchkin * 4*031542fcSKonstantin Porotchkin * SPDX-License-Identifier: BSD-3-Clause 5*031542fcSKonstantin Porotchkin * https://spdx.org/licenses 6*031542fcSKonstantin Porotchkin */ 7*031542fcSKonstantin Porotchkin 8*031542fcSKonstantin Porotchkin /* CP110 Marvell SoC driver */ 9*031542fcSKonstantin Porotchkin 10*031542fcSKonstantin Porotchkin #ifndef __CP110_SETUP_H__ 11*031542fcSKonstantin Porotchkin #define __CP110_SETUP_H__ 12*031542fcSKonstantin Porotchkin 13*031542fcSKonstantin Porotchkin #include <mmio.h> 14*031542fcSKonstantin Porotchkin #include <mvebu_def.h> 15*031542fcSKonstantin Porotchkin 16*031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_ID_REG (MVEBU_CP_DFX_OFFSET + 0x40) 17*031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_ID_OFFSET (0) 18*031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_ID_MASK (0xffff << MVEBU_DEVICE_ID_OFFSET) 19*031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_REV_OFFSET (16) 20*031542fcSKonstantin Porotchkin #define MVEBU_DEVICE_REV_MASK (0xf << MVEBU_DEVICE_REV_OFFSET) 21*031542fcSKonstantin Porotchkin #define MVEBU_70X0_DEV_ID (0x7040) 22*031542fcSKonstantin Porotchkin #define MVEBU_70X0_CP115_DEV_ID (0x7045) 23*031542fcSKonstantin Porotchkin #define MVEBU_80X0_DEV_ID (0x8040) 24*031542fcSKonstantin Porotchkin #define MVEBU_80X0_CP115_DEV_ID (0x8045) 25*031542fcSKonstantin Porotchkin #define MVEBU_CP110_SA_DEV_ID (0x110) 26*031542fcSKonstantin Porotchkin #define MVEBU_CP110_REF_ID_A1 1 27*031542fcSKonstantin Porotchkin #define MVEBU_CP110_REF_ID_A2 2 28*031542fcSKonstantin Porotchkin #define MAX_STREAM_ID_PER_CP (0x10) 29*031542fcSKonstantin Porotchkin #define STREAM_ID_BASE (0x40) 30*031542fcSKonstantin Porotchkin 31*031542fcSKonstantin Porotchkin static inline uint32_t cp110_device_id_get(uintptr_t base) 32*031542fcSKonstantin Porotchkin { 33*031542fcSKonstantin Porotchkin /* Returns: 34*031542fcSKonstantin Porotchkin * - MVEBU_70X0_DEV_ID for A70X0 family 35*031542fcSKonstantin Porotchkin * - MVEBU_80X0_DEV_ID for A80X0 family 36*031542fcSKonstantin Porotchkin * - MVEBU_CP110_SA_DEV_ID for CP that connected stand alone 37*031542fcSKonstantin Porotchkin */ 38*031542fcSKonstantin Porotchkin return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) >> 39*031542fcSKonstantin Porotchkin MVEBU_DEVICE_ID_OFFSET) & 40*031542fcSKonstantin Porotchkin MVEBU_DEVICE_ID_MASK; 41*031542fcSKonstantin Porotchkin } 42*031542fcSKonstantin Porotchkin 43*031542fcSKonstantin Porotchkin static inline uint32_t cp110_rev_id_get(uintptr_t base) 44*031542fcSKonstantin Porotchkin { 45*031542fcSKonstantin Porotchkin return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) & 46*031542fcSKonstantin Porotchkin MVEBU_DEVICE_REV_MASK) >> 47*031542fcSKonstantin Porotchkin MVEBU_DEVICE_REV_OFFSET; 48*031542fcSKonstantin Porotchkin } 49*031542fcSKonstantin Porotchkin 50*031542fcSKonstantin Porotchkin void cp110_init(uintptr_t cp110_base, uint32_t stream_id); 51*031542fcSKonstantin Porotchkin void cp110_ble_init(uintptr_t cp110_base); 52*031542fcSKonstantin Porotchkin 53*031542fcSKonstantin Porotchkin #endif /* __CP110_SETUP_H__ */ 54