1 /* 2 * Copyright (C) 2017 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 #ifndef ARO_H 8 #define ARO_H 9 10 enum hws_freq { 11 CPU_FREQ_2000, 12 CPU_FREQ_1800, 13 CPU_FREQ_1600, 14 CPU_FREQ_1400, 15 CPU_FREQ_1300, 16 CPU_FREQ_1200, 17 CPU_FREQ_1000, 18 CPU_FREQ_600, 19 CPU_FREQ_800, 20 DDR_FREQ_LAST, 21 DDR_FREQ_SAR 22 }; 23 24 #include <mvebu_def.h> 25 26 enum cpu_clock_freq_mode { 27 CPU_2000_DDR_1200_RCLK_1200 = 0x0, 28 CPU_2000_DDR_1050_RCLK_1050 = 0x1, 29 CPU_1600_DDR_800_RCLK_800 = 0x4, 30 #ifdef MVEBU_SOC_AP807 31 CPU_2200_DDR_1200_RCLK_1200 = 0x6, 32 #else 33 CPU_1800_DDR_1200_RCLK_1200 = 0x6, 34 #endif 35 CPU_1800_DDR_1050_RCLK_1050 = 0x7, 36 CPU_1600_DDR_900_RCLK_900 = 0x0B, 37 CPU_1600_DDR_1050_RCLK_1050 = 0x0D, 38 CPU_1600_DDR_1200_RCLK_1200 = 0x0D, 39 CPU_1600_DDR_900_RCLK_900_2 = 0x0E, 40 CPU_1000_DDR_650_RCLK_650 = 0x13, 41 CPU_1300_DDR_800_RCLK_800 = 0x14, 42 CPU_1300_DDR_650_RCLK_650 = 0x17, 43 CPU_1200_DDR_800_RCLK_800 = 0x19, 44 CPU_1400_DDR_800_RCLK_800 = 0x1a, 45 CPU_600_DDR_800_RCLK_800 = 0x1B, 46 CPU_800_DDR_800_RCLK_800 = 0x1C, 47 CPU_1000_DDR_800_RCLK_800 = 0x1D, 48 CPU_DDR_RCLK_INVALID 49 }; 50 51 int init_aro(void); 52 53 #endif /* ARO_H */ 54