1 /* 2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CDN_NAND_H 9 #define CDN_NAND_H 10 11 #include <drivers/cadence/cdns_combo_phy.h> 12 13 // TBD: Move to common place 14 #define __bf_shf(x) (__builtin_ffsll(x) - 1U) 15 #define FIELD_GET(_mask, _reg) \ 16 ({ \ 17 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ 18 }) 19 20 #define FIELD_PREP(_mask, _val) \ 21 ({ \ 22 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ 23 }) 24 25 /* NAND flash device information */ 26 typedef struct cnf_dev_info { 27 uint8_t mfr_id; 28 uint8_t dev_id; 29 uint8_t type; 30 uint8_t nluns; 31 uint8_t sector_cnt; 32 uint16_t npages_per_block; 33 uint16_t sector_size; 34 uint16_t last_sector_size; 35 uint16_t page_size; 36 uint16_t spare_size; 37 uint32_t nblocks_per_lun; 38 uint32_t block_size; 39 unsigned long long total_size; 40 } cnf_dev_info_t; 41 42 /* Shared Macros */ 43 44 /* Default values */ 45 #define CNF_DEF_VOL_ID 0 46 #define CNF_DEF_DEVICE 0 47 #define CNF_DEF_TRD 0 48 #define CNF_READ_SINGLE_PAGE 1U 49 #define CNF_DEF_DELAY_US 500U 50 #define CNF_READ_INT_DELAY_US 10U 51 52 /* Number of micro seconds to complete the Device Discovery Process. */ 53 #define CNF_DD_INIT_COMP_US 2000000U 54 55 /* Work modes */ 56 #define CNF_WORK_MODE_CDMA 0U 57 #define CNF_WORK_MODE_PIO 1U 58 59 /* Command types */ 60 #define CNF_CT_SET_FEATURE 0x0100 61 #define CNF_CT_RESET_ASYNC 0x1100 62 #define CNF_CT_RESET_SYNC 0x1101 63 #define CNF_CT_RESET_LUN 0x1102 64 #define CNF_CT_ERASE 0x1000 65 #define CNF_CT_PAGE_PROGRAM 0x2100 66 #define CNF_CT_PAGE_READ 0x2200 67 68 /* Interrupts enable or disable */ 69 #define CNF_INT_EN 1U 70 #define CNF_INT_DIS 0U 71 72 /* Device types */ 73 #define CNF_DT_UNKNOWN 0x00 74 #define CNF_DT_ONFI 0x01 75 #define CNF_DT_JEDEC 0x02 76 #define CNF_DT_LEGACY 0x03 77 78 /* Command and status registers */ 79 #define CNF_CMDREG_REG_BASE SOCFPGA_NAND_REG_BASE 80 81 /* DMA maximum burst size 0-127*/ 82 #define CNF_DMA_BURST_SIZE_MAX 127U 83 84 /* DMA settings register field offsets */ 85 #define CNF_DMA_SETTINGS_BURST 0U 86 #define CNF_DMA_SETTINGS_OTE 16U 87 #define CNF_DMA_SETTINGS_SDMA_ER 17U 88 89 #define CNF_DMA_MASTER_SEL 1U 90 #define CNF_DMA_SLAVE_SEL 0U 91 92 /* DMA FIFO trigger level register field offsets */ 93 #define CNF_FIFO_TLEVEL_POS 0U 94 #define CNF_FIFO_TLEVEL_DMA_SIZE 16U 95 #define CNF_DMA_PREFETCH_SIZE (1024 / 8) 96 97 #define CNF_GET_CTRL_BUSY(x) (x & (1 << 8)) 98 #define CNF_GET_INIT_COMP(x) (x & (1 << 9)) 99 100 /* Command register0 field offsets */ 101 #define CNF_CMDREG0_CT 30U 102 #define CNF_CMDREG0_TRD 24U 103 #define CNF_CMDREG0_INTR 20U 104 #define CNF_CMDREG0_DMA 21U 105 #define CNF_CMDREG0_VOL 16U 106 #define CNF_CMDREG0_CMD 0U 107 #define CNF_CMDREG4_MEM 24U 108 109 /* Command status register field offsets */ 110 #define CNF_ECMD BIT(0) 111 #define CNF_EECC BIT(1) 112 #define CNF_EMAX BIT(2) 113 #define CNF_EDEV BIT(12) 114 #define CNF_EDQS BIT(13) 115 #define CNF_EFAIL BIT(14) 116 #define CNF_CMPLT BIT(15) 117 #define CNF_EBUS BIT(16) 118 #define CNF_EDI BIT(17) 119 #define CNF_EPAR BIT(18) 120 #define CNF_ECTX BIT(19) 121 #define CNF_EPRO BIT(20) 122 #define CNF_EIDX BIT(24) 123 124 #define CNF_CMDREG_CMD_REG0 0x00 125 #define CNF_CMDREG_CMD_REG1 0x04 126 #define CNF_CMDREG_CMD_REG2 0x08 127 #define CNF_CMDREG_CMD_REG3 0x0C 128 #define CNF_CMDREG_CMD_STAT_PTR 0x10 129 #define CNF_CMDREG_CMD_STAT 0x14 130 #define CNF_CMDREG_CMD_REG4 0x20 131 #define CNF_CMDREG_CTRL_STATUS 0x118 132 #define CNF_CMDREG_TRD_STATUS 0x120 133 134 #define CNF_CMDREG(_reg) (CNF_CMDREG_REG_BASE \ 135 + (CNF_CMDREG_##_reg)) 136 137 /* Controller configuration registers */ 138 #define CNF_LSB16_MASK 0xFFFF 139 #define CNF_GET_NPAGES_PER_BLOCK(x) (x & CNF_LSB16_MASK) 140 141 #define CNF_GET_SCTR_SIZE(x) (x & CNF_LSB16_MASK) 142 #define CNF_GET_LAST_SCTR_SIZE(x) ((x >> 16) & CNF_LSB16_MASK) 143 144 #define CNF_GET_PAGE_SIZE(x) (x & CNF_LSB16_MASK) 145 #define CNF_GET_SPARE_SIZE(x) ((x >> 16) & CNF_LSB16_MASK) 146 147 #define CNF_CTRLCFG_REG_BASE 0x10B80400 148 #define CNF_CTRLCFG_TRANS_CFG0 0x00 149 #define CNF_CTRLCFG_TRANS_CFG1 0x04 150 #define CNF_CTRLCFG_LONG_POLL 0x08 151 #define CNF_CTRLCFG_SHORT_POLL 0x0C 152 #define CNF_CTRLCFG_RDST_CTRL_0 0x10 153 #define CNF_CTRLCFG_DEV_LAYOUT 0x24 154 #define CNF_CTRLCFG_ECC_CFG0 0x28 155 #define CNF_CTRLCFG_ECC_CFG1 0x2C 156 #define CNF_CTRLCFG_MULTIPLANE_CFG 0x34 157 #define CNF_CTRLCFG_CACHE_CFG 0x38 158 #define CNF_CTRLCFG_DMA_SETTINGS 0x3C 159 #define CNF_CTRLCFG_FIFO_TLEVEL 0x54 160 161 #define CNF_ECC_EN BIT(0) 162 #define CNF_ECC_ERASE_DET_EN BIT(1) 163 #define CNF_ECC_CORR_STR_MASK GENMASK(10, 8) 164 #define CNF_ECC_CORR_STR 0x02 165 166 #define CNF_ECC_CFG0_VAL ((CNF_ECC_EN) | \ 167 (CNF_ECC_ERASE_DET_EN) | \ 168 (FIELD_PREP(CNF_ECC_CORR_STR_MASK, CNF_ECC_CORR_STR))) 169 170 /* Transfer configuration 0 and 1 register settings. */ 171 #define CNF_SECTOR_CNT 0x04 172 #define CNF_SECTOR_OFFSET_MASK GENMASK(31, 16) 173 #define CNF_SECTOR_OFFSET 0x00 174 175 #define CNF_TRANS_CFG0_VAL ((CNF_SECTOR_CNT) | \ 176 (FIELD_PREP(CNF_SECTOR_OFFSET_MASK, CNF_SECTOR_OFFSET))) 177 178 #define CNF_SECTOR_SIZE 0x0800 179 #define CNF_LAST_SECTOR_MASK GENMASK(31, 16) 180 #define CNF_LAST_SECTOR_SIZE 0x0828 181 182 #define CNF_TRANS_CFG1_VAL ((CNF_SECTOR_SIZE) | \ 183 (FIELD_PREP(CNF_LAST_SECTOR_MASK, CNF_LAST_SECTOR_SIZE))) 184 185 186 #define CNF_CTRLCFG(_reg) (CNF_CTRLCFG_REG_BASE \ 187 + (CNF_CTRLCFG_##_reg)) 188 189 /* Data integrity registers */ 190 #define CNF_DI_PAR_EN 0U 191 #define CNF_DI_CRC_EN 1U 192 193 #define CNF_DI_REG_BASE 0x10B80700 194 #define CNF_DI_CONTROL 0x00 195 #define CNF_DI_INJECT0 0x04 196 #define CNF_DI_INJECT1 0x08 197 #define CNF_DI_ERR_REG_ADDR 0x0C 198 #define CNF_DI_INJECT2 0x10 199 200 #define CNF_DI(_reg) (CNF_DI_REG_BASE \ 201 + (CNF_DI_##_reg)) 202 203 /* Controller parameter registers */ 204 #define CNF_NTHREADS_MASK 0x07 205 #define CNF_GET_NLUNS(x) (x & 0xFF) 206 #define CNF_GET_DEV_TYPE(x) ((x >> 30) & 0x03) 207 #define CNF_GET_NTHREADS(x) (1 << (x & CNF_NTHREADS_MASK)) 208 209 #define CNF_CTRLPARAM_REG_BASE 0x10B80800 210 #define CNF_CTRLPARAM_VERSION 0x00 211 #define CNF_CTRLPARAM_FEATURE 0x04 212 #define CNF_CTRLPARAM_MFR_ID 0x08 213 #define CNF_CTRLPARAM_DEV_AREA 0x0C 214 #define CNF_CTRLPARAM_DEV_PARAMS0 0x10 215 #define CNF_CTRLPARAM_DEV_PARAMS1 0x14 216 #define CNF_CTRLPARAM_DEV_FEATUERS 0x18 217 #define CNF_CTRLPARAM_DEV_BLOCKS_PLUN 0x1C 218 219 #define CNF_MFR_ID_MASK GENMASK(7, 0) 220 #define CNF_DEV_ID_MASK GENMASK(23, 16) 221 222 #define CNF_CTRLPARAM(_reg) (CNF_CTRLPARAM_REG_BASE \ 223 + (CNF_CTRLPARAM_##_reg)) 224 225 /* Protection mechanism registers */ 226 #define CNF_PROT_REG_BASE 0x10B80900 227 #define CNF_PROT_CTRL0 0x00 228 #define CNF_PROT_DOWN0 0x04 229 #define CNF_PROT_UP0 0x08 230 #define CNF_PROT_CTRL1 0x10 231 #define CNF_PROT_DOWN1 0x14 232 #define CNF_PROT_UP1 0x18 233 234 #define CNF_PROT(_reg) (CNF_PROT_REG_BASE \ 235 + (CNF_PROT_##_reg)) 236 237 /* Mini controller registers */ 238 #define CNF_MINICTRL_REG_BASE 0x10B81000 239 240 /* Operation work modes */ 241 #define CNF_OPR_WORK_MODE_SDR 0U 242 #define CNF_OPR_WORK_MODE_NVDDR 1U 243 #define CNF_OPR_WORK_MODE_RES 3U 244 245 /* Mini controller common settings register field offsets */ 246 #define CNF_CMN_SETTINGS_OPR_MASK 0x00000003 247 #define CNF_CMN_SETTINGS_WR_WUP 20U 248 #define CNF_CMN_SETTINGS_RD_WUP 16U 249 #define CNF_CMN_SETTINGS_DEV16 8U 250 #define CNF_CMN_SETTINGS_OPR 0U 251 252 /* Async mode register field offsets */ 253 #define CNF_ASYNC_TIMINGS_TRH 24U 254 #define CNF_ASYNC_TIMINGS_TRP 16U 255 #define CNF_ASYNC_TIMINGS_TWH 8U 256 #define CNF_ASYNC_TIMINGS_TWP 0U 257 258 /* 259 * The number of clock cycles (nf_clk) the mini controller needs to 260 * assert/de-assert WE# and assert/de-assert RE# signals in SDR asynchronous mode. 261 */ 262 #define CNF_ASYNC_NCLOCK_CYCLES 0x09 263 #define CNF_ASYNC_TOGGLE_TIMINGS_VAL ((CNF_ASYNC_NCLOCK_CYCLES << CNF_ASYNC_TIMINGS_TRH) | \ 264 (CNF_ASYNC_NCLOCK_CYCLES << CNF_ASYNC_TIMINGS_TRP) | \ 265 (CNF_ASYNC_NCLOCK_CYCLES << CNF_ASYNC_TIMINGS_TWH) | \ 266 (CNF_ASYNC_NCLOCK_CYCLES << CNF_ASYNC_TIMINGS_TWP)) 267 268 /* 269 * Default value from the datasheet: The number of clock cycles (nf_clk) between 270 * the de-assertion of the DLL update request and resuming traffic to the PHY. 271 */ 272 #define RESYNC_IDLE_CNT 0x07 273 #define RESYNC_IDLE_CNT_MASK GENMASK(7, 0) 274 275 /* 276 * Default value from the datasheet: The number of clock cycles (nf_clk) for which 277 * the DLL update request has to be asserted, to resynchronize the DLLs and read 278 * and write FIFO pointers. 279 */ 280 #define RESYNC_HIGH_CNT 0x07 281 #define RESYNC_HIGH_CNT_MASK GENMASK(11, 8) 282 283 #define CNF_DLL_PHY_RST_N BIT(24) 284 #define CNF_DLL_PHY_EXT_WR_MODE BIT(17) 285 #define CNF_DLL_PHY_EXT_RD_MODE BIT(16) 286 287 #define CNF_DLL_PHY_CTRL_VAL ((CNF_DLL_PHY_RST_N) | \ 288 (CNF_DLL_PHY_EXT_WR_MODE) | \ 289 (CNF_DLL_PHY_EXT_RD_MODE) | \ 290 (FIELD_PREP(RESYNC_IDLE_CNT_MASK, RESYNC_IDLE_CNT)) | \ 291 (FIELD_PREP(RESYNC_HIGH_CNT_MASK, RESYNC_HIGH_CNT))) 292 293 /* Global timings configurations */ 294 #define CNF_MINICTRL_TIMINGS0_VAL 0x4f631727 295 #define CNF_MINICTRL_TIMINGS1_VAL 0x28300063 296 #define CNF_MINICTRL_TIMINGS2_VAL 0x00c7030d 297 298 /* Mini controller DLL PHY controller register field offsets */ 299 #define CNF_MINICTRL_WP_SETTINGS 0x00 300 #define CNF_MINICTRL_RBN_SETTINGS 0x04 301 #define CNF_MINICTRL_CMN_SETTINGS 0x08 302 #define CNF_MINICTRL_SKIP_BYTES_CFG 0x0C 303 #define CNF_MINICTRL_SKIP_BYTES_OFFSET 0x10 304 #define CNF_MINICTRL_TOGGLE_TIMINGS0 0x14 305 #define CNF_MINICTRL_TOGGLE_TIMINGS1 0x18 306 #define CNF_MINICTRL_ASYNC_TOGGLE_TIMINGS 0x1C 307 #define CNF_MINICTRL_SYNC_TIMINGS 0x20 308 #define CNF_MINICTRL_TIMINGS0 0x24 309 #define CNF_MINICTRL_TIMINGS1 0x28 310 #define CNF_MINICTRL_TIMINGS2 0x2C 311 #define CNF_MINICTRL_DLL_PHY_UPDATE_CNT 0x30 312 #define CNF_MINICTRL_DLL_PHY_CTRL 0x34 313 314 /* 315 * Number of bytes to skip from offset of block. 316 * The bytes are written with the value programmed in the marker field. 317 */ 318 #define CNF_NSKIP_BYTES 0x02 319 #define CNF_MARKER_VAL 0xFFFF 320 #define CNF_MARKER_MASK GENMASK(31, 16) 321 #define CNF_SKIP_BYTES_CFG_VAL ((CNF_NSKIP_BYTES) | \ 322 (FIELD_PREP(CNF_MARKER_MASK, CNF_MARKER_VAL))) 323 324 /* Offset after which the controller starts sending the dummy bytest to the device. */ 325 #define CNF_SKIP_BYTES_OFFSET_VAL (0x00002000) 326 327 #define CNF_MINICTRL(_reg) (CNF_MINICTRL_REG_BASE \ 328 + (CNF_MINICTRL_##_reg)) 329 330 /* 331 * @brief Nand IO MTD initialization routine 332 * 333 * @total_size: [out] Total size of the NAND flash device 334 * @erase_size: [out] Minimum erase size of the NAND flash device 335 * Return: 0 on success, a negative errno on failure 336 */ 337 int cdns_nand_init_mtd(unsigned long long *total_size, unsigned int *erase_size); 338 339 /* 340 * @brief Read bytes from the NAND flash device 341 * 342 * @offset: Byte offset to read from in device 343 * @buffer: [out] Bytes read from device 344 * @length: Number of bytes to read 345 * @out_length: [out] Number of bytes read from device 346 * Return: 0 on success, a negative errno on failure 347 */ 348 int cdns_nand_read(unsigned int offset, uintptr_t buffer, size_t length, size_t *out_length); 349 350 /* 351 * @brief NAND Flash Controller/Host initialization 352 * Return: 0 on success, a negative errno on failure 353 */ 354 int cdns_nand_host_init(void); 355 356 #endif 357