1*441a065aSBharat Gooty /* 2*441a065aSBharat Gooty * Copyright (c) 2016 - 2021, Broadcom 3*441a065aSBharat Gooty * 4*441a065aSBharat Gooty * SPDX-License-Identifier: BSD-3-Clause 5*441a065aSBharat Gooty */ 6*441a065aSBharat Gooty 7*441a065aSBharat Gooty #ifndef MDIO_H 8*441a065aSBharat Gooty #define MDIO_H 9*441a065aSBharat Gooty 10*441a065aSBharat Gooty #define CMIC_MIIM_PARAM (PLAT_CMIC_MIIM_BASE + 0x23cU) 11*441a065aSBharat Gooty #define MDIO_PARAM_MIIM_CYCLE 29U 12*441a065aSBharat Gooty #define MDIO_PARAM_INTERNAL_SEL 25U 13*441a065aSBharat Gooty #define MDIO_PARAM_BUSID 22U 14*441a065aSBharat Gooty #define MDIO_PARAM_BUSID_MASK 0x7U 15*441a065aSBharat Gooty #define MDIO_PARAM_C45_SEL 21U 16*441a065aSBharat Gooty #define MDIO_PARAM_PHYID 16U 17*441a065aSBharat Gooty #define MDIO_PARAM_PHYID_MASK 0x1FU 18*441a065aSBharat Gooty #define MDIO_PARAM_DATA 0U 19*441a065aSBharat Gooty #define MDIO_PARAM_DATA_MASK 0xFFFFU 20*441a065aSBharat Gooty #define CMIC_MIIM_READ_DATA (PLAT_CMIC_MIIM_BASE + 0x240U) 21*441a065aSBharat Gooty #define MDIO_READ_DATA_MASK 0xffffU 22*441a065aSBharat Gooty #define CMIC_MIIM_ADDRESS (PLAT_CMIC_MIIM_BASE + 0x244U) 23*441a065aSBharat Gooty #define CMIC_MIIM_CTRL (PLAT_CMIC_MIIM_BASE + 0x248U) 24*441a065aSBharat Gooty #define MDIO_CTRL_WRITE_OP 0x1U 25*441a065aSBharat Gooty #define MDIO_CTRL_READ_OP 0x2U 26*441a065aSBharat Gooty #define CMIC_MIIM_STAT (PLAT_CMIC_MIIM_BASE + 0x24cU) 27*441a065aSBharat Gooty #define MDIO_STAT_DONE 1U 28*441a065aSBharat Gooty 29*441a065aSBharat Gooty int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val); 30*441a065aSBharat Gooty int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg); 31*441a065aSBharat Gooty #endif /* MDIO_H */ 32