1*9a40c0fbSSheetal Tigadoli /* 2*9a40c0fbSSheetal Tigadoli * Copyright (c) 2015 - 2020, Broadcom 3*9a40c0fbSSheetal Tigadoli * 4*9a40c0fbSSheetal Tigadoli * SPDX-License-Identifier: BSD-3-Clause 5*9a40c0fbSSheetal Tigadoli */ 6*9a40c0fbSSheetal Tigadoli 7*9a40c0fbSSheetal Tigadoli #ifndef DMU_H 8*9a40c0fbSSheetal Tigadoli #define DMU_H 9*9a40c0fbSSheetal Tigadoli 10*9a40c0fbSSheetal Tigadoli /* Clock field should be 2 bits only */ 11*9a40c0fbSSheetal Tigadoli #define CLKCONFIG_MASK 0x3 12*9a40c0fbSSheetal Tigadoli 13*9a40c0fbSSheetal Tigadoli /* argument */ 14*9a40c0fbSSheetal Tigadoli struct DmuBlockEnable { 15*9a40c0fbSSheetal Tigadoli uint32_t sotp:1; 16*9a40c0fbSSheetal Tigadoli uint32_t pka_rng:1; 17*9a40c0fbSSheetal Tigadoli uint32_t crypto:1; 18*9a40c0fbSSheetal Tigadoli uint32_t spl:1; 19*9a40c0fbSSheetal Tigadoli uint32_t cdru_vgm:1; 20*9a40c0fbSSheetal Tigadoli uint32_t apbs_s0_idm:1; 21*9a40c0fbSSheetal Tigadoli uint32_t smau_s0_idm:1; 22*9a40c0fbSSheetal Tigadoli }; 23*9a40c0fbSSheetal Tigadoli 24*9a40c0fbSSheetal Tigadoli /* prototype */ 25*9a40c0fbSSheetal Tigadoli uint32_t bcm_dmu_block_enable(struct DmuBlockEnable dbe); 26*9a40c0fbSSheetal Tigadoli uint32_t bcm_dmu_block_disable(struct DmuBlockEnable dbe); 27*9a40c0fbSSheetal Tigadoli uint32_t bcm_set_ihost_pll_freq(uint32_t cluster_num, int ihost_pll_freq_sel); 28*9a40c0fbSSheetal Tigadoli uint32_t bcm_get_ihost_pll_freq(uint32_t cluster_num); 29*9a40c0fbSSheetal Tigadoli 30*9a40c0fbSSheetal Tigadoli #define PLL_FREQ_BYPASS 0x0 31*9a40c0fbSSheetal Tigadoli #define PLL_FREQ_FULL 0x1 32*9a40c0fbSSheetal Tigadoli #define PLL_FREQ_HALF 0x2 33*9a40c0fbSSheetal Tigadoli #define PLL_FREQ_QRTR 0x3 34*9a40c0fbSSheetal Tigadoli 35*9a40c0fbSSheetal Tigadoli #endif 36