1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TZC_DMC500_H__ 32 #define __TZC_DMC500_H__ 33 34 #include <tzc_common.h> 35 36 #define SI_STATUS_OFFSET 0x000 37 #define SI_STATE_CTRL_OFFSET 0x030 38 #define SI_FLUSH_CTRL_OFFSET 0x034 39 #define SI_INT_CONTROL_OFFSET 0x048 40 41 #define SI_INT_STATUS_OFFSET 0x004 42 #define SI_TZ_FAIL_ADDRESS_LOW_OFFSET 0x008 43 #define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET 0x00c 44 #define SI_FAIL_CONTROL_OFFSET 0x010 45 #define SI_FAIL_ID_OFFSET 0x014 46 #define SI_INT_CLR_OFFSET 0x04c 47 48 /* 49 * DMC-500 has 2 system interfaces each having a similar set of regs 50 * to configure each interface. 51 */ 52 #define SI0_BASE 0x0000 53 #define SI1_BASE 0x0200 54 55 /* Bit positions of SIx_SI_STATUS */ 56 #define SI_EMPTY_SHIFT 0x01 57 #define SI_STALL_ACK_SHIFT 0x00 58 #define SI_EMPTY_MASK 0x01 59 #define SI_STALL_ACK_MASK 0x01 60 61 /* Bit positions of SIx_SI_INT_STATUS */ 62 #define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18 63 #define FAILED_ACCESS_INT_OVERFLOW_STATUS_SHIFT 16 64 #define PMU_REQ_INT_STATUS_SHIFT 2 65 #define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1 66 #define FAILED_ACCESS_INT_STATUS_SHIFT 0 67 #define PMU_REQ_INT_OVERFLOW_STATUS_MASK 0x1 68 #define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK 0x1 69 #define PMU_REQ_INT_STATUS_MASK 0x1 70 #define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK 0x1 71 #define FAILED_ACCESS_INT_STATUS_MASK 0x1 72 73 /* Bit positions of SIx_TZ_FAIL_CONTROL */ 74 #define DIRECTION_SHIFT 24 75 #define NON_SECURE_SHIFT 21 76 #define PRIVILEGED_SHIFT 20 77 #define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3 78 #define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2 79 #define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 0x1 80 #define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0 81 #define DIRECTION_MASK 0x1 82 #define NON_SECURE_MASK 0x1 83 #define PRIVILEGED_MASK 0x1 84 #define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK 0x1 85 #define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK 0x1 86 #define FAILED_ACCESS_INT_TZ_FAIL_MASK 1 87 #define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK 0x1 88 89 /* Bit positions of SIx_FAIL_STATUS */ 90 #define FAIL_ID_VNET_SHIFT 24 91 #define FAIL_ID_ID_SHIFT 0 92 #define FAIL_ID_VNET_MASK 0xf 93 #define FAIL_ID_ID_MASK 0xffffff 94 95 /* Bit positions of SIx_SI_STATE_CONTRL */ 96 #define SI_STALL_REQ_GO 0x0 97 #define SI_STALL_REQ_STALL 0x1 98 99 /* Bit positions of SIx_SI_FLUSH_CONTROL */ 100 #define SI_FLUSH_REQ_INACTIVE 0x0 101 #define SI_FLUSH_REQ_ACTIVE 0x1 102 #define SI_FLUSH_REQ_MASK 0x1 103 104 /* Bit positions of SIx_SI_INT_CONTROL */ 105 #define PMU_REQ_INT_EN_SHIFT 2 106 #define OVERLAP_DETECT_INT_EN_SHIFT 1 107 #define FAILED_ACCESS_INT_EN_SHIFT 0 108 #define PMU_REQ_INT_EN_MASK 0x1 109 #define OVERLAP_DETECT_INT_EN_MASK 0x1 110 #define FAILED_ACCESS_INT_EN_MASK 0x1 111 #define PMU_REQ_INT_EN 0x1 112 #define OVERLAP_DETECT_INT_EN 0x1 113 #define FAILED_ACCESS_INT_EN 0x1 114 115 /* Bit positions of SIx_SI_INT_CLR */ 116 #define PMU_REQ_OFLOW_CLR_SHIFT 18 117 #define FAILED_ACCESS_OFLOW_CLR_SHIFT 16 118 #define PMU_REQ_INT_CLR_SHIFT 2 119 #define FAILED_ACCESS_INT_CLR_SHIFT 0 120 #define PMU_REQ_OFLOW_CLR_MASK 0x1 121 #define FAILED_ACCESS_OFLOW_CLR_MASK 0x1 122 #define PMU_REQ_INT_CLR_MASK 0x1 123 #define FAILED_ACCESS_INT_CLR_MASK 0x1 124 #define PMU_REQ_OFLOW_CLR 0x1 125 #define FAILED_ACCESS_OFLOW_CLR 0x1 126 #define PMU_REQ_INT_CLR 0x1 127 #define FAILED_ACCESS_INT_CLR 0x1 128 129 /* Macro to get the correct base register for a system interface */ 130 #define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE) 131 132 #define MAX_SYS_IF_COUNT 2 133 #define MAX_REGION_VAL 8 134 135 /* DMC-500 supports striping across a max of 4 DMC instances */ 136 #define MAX_DMC_COUNT 4 137 138 /* Consist of part_number_1 and part_number_0 */ 139 #define DMC500_PERIPHERAL_ID 0x0450 140 141 /* Filter enable bits in a TZC */ 142 #define TZC_DMC500_REGION_ATTR_F_EN_MASK 0x1 143 144 /* Length of registers for configuring each region */ 145 #define TZC_DMC500_REGION_SIZE 0x018 146 147 #ifndef __ASSEMBLY__ 148 149 #include <stdint.h> 150 151 /* 152 * Contains the base addresses of all the DMC instances. 153 */ 154 typedef struct tzc_dmc500_driver_data { 155 uintptr_t dmc_base[MAX_DMC_COUNT]; 156 int dmc_count; 157 } tzc_dmc500_driver_data_t; 158 159 void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data); 160 void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr, 161 unsigned int nsaid_permissions); 162 void tzc_dmc500_configure_region(int region_no, 163 unsigned long long region_base, 164 unsigned long long region_top, 165 tzc_region_attributes_t sec_attr, 166 unsigned int nsaid_permissions); 167 void tzc_dmc500_set_action(tzc_action_t action); 168 void tzc_dmc500_config_complete(void); 169 int tzc_dmc500_verify_complete(void); 170 171 172 #endif /* __ASSEMBLY__ */ 173 #endif /* __TZC_DMC500_H__ */ 174 175