1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TZC_COMMON_H__ 32 #define __TZC_COMMON_H__ 33 34 /* 35 * Offset of core registers from the start of the base of configuration 36 * registers for each region. 37 */ 38 39 /* ID Registers */ 40 #define PID0_OFF 0xfe0 41 #define PID1_OFF 0xfe4 42 #define PID2_OFF 0xfe8 43 #define PID3_OFF 0xfec 44 #define PID4_OFF 0xfd0 45 #define CID0_OFF 0xff0 46 #define CID1_OFF 0xff4 47 #define CID2_OFF 0xff8 48 #define CID3_OFF 0xffc 49 50 /* Bit positions of TZC_ACTION registers */ 51 #define TZC_ACTION_RV_SHIFT 0 52 #define TZC_ACTION_RV_MASK 0x3 53 #define TZC_ACTION_RV_LOWOK 0x0 54 #define TZC_ACTION_RV_LOWERR 0x1 55 #define TZC_ACTION_RV_HIGHOK 0x2 56 #define TZC_ACTION_RV_HIGHERR 0x3 57 58 /* Used along with 'tzc_region_attributes_t' below */ 59 #define TZC_REGION_ATTR_S_RD_SHIFT 30 60 #define TZC_REGION_ATTR_S_WR_SHIFT 31 61 #define TZC_REGION_ATTR_F_EN_SHIFT 0 62 #define TZC_REGION_ATTR_SEC_SHIFT 30 63 #define TZC_REGION_ATTR_S_RD_MASK 0x1 64 #define TZC_REGION_ATTR_S_WR_MASK 0x1 65 #define TZC_REGION_ATTR_SEC_MASK 0x3 66 67 #define TZC_REGION_ACCESS_WR_EN_SHIFT 16 68 #define TZC_REGION_ACCESS_RD_EN_SHIFT 0 69 #define TZC_REGION_ACCESS_ID_MASK 0xf 70 71 /* Macros for allowing Non-Secure access to a region based on NSAID */ 72 #define TZC_REGION_ACCESS_RD(nsaid) \ 73 ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \ 74 TZC_REGION_ACCESS_RD_EN_SHIFT) 75 #define TZC_REGION_ACCESS_WR(nsaid) \ 76 ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \ 77 TZC_REGION_ACCESS_WR_EN_SHIFT) 78 #define TZC_REGION_ACCESS_RDWR(nsaid) \ 79 (TZC_REGION_ACCESS_RD(nsaid) | \ 80 TZC_REGION_ACCESS_WR(nsaid)) 81 82 #ifndef __ASSEMBLY__ 83 84 /* Returns offset of registers to program for a given region no */ 85 #define TZC_REGION_OFFSET(region_size, region_no) \ 86 ((region_size) * (region_no)) 87 88 /* 89 * What type of action is expected when an access violation occurs. 90 * The memory requested is returned as zero. But we can also raise an event to 91 * let the system know it happened. 92 * We can raise an interrupt(INT) and/or cause an exception(ERR). 93 * TZC_ACTION_NONE - No interrupt, no Exception 94 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 95 * data abort 96 * TZC_ACTION_INT - Raise interrupt, no exception 97 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 98 * external data abort 99 */ 100 typedef enum { 101 TZC_ACTION_NONE = 0, 102 TZC_ACTION_ERR = 1, 103 TZC_ACTION_INT = 2, 104 TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) 105 } tzc_action_t; 106 107 /* 108 * Controls secure access to a region. If not enabled secure access is not 109 * allowed to region. 110 */ 111 typedef enum { 112 TZC_REGION_S_NONE = 0, 113 TZC_REGION_S_RD = 1, 114 TZC_REGION_S_WR = 2, 115 TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) 116 } tzc_region_attributes_t; 117 118 #endif /* __ASSEMBLY__ */ 119 #endif /* __TZC_COMMON_H__ */ 120