1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TZC400_H__ 32 #define __TZC400_H__ 33 34 35 #define BUILD_CONFIG_OFF 0x000 36 #define ACTION_OFF 0x004 37 #define GATE_KEEPER_OFF 0x008 38 #define SPECULATION_CTRL_OFF 0x00c 39 #define INT_STATUS 0x010 40 #define INT_CLEAR 0x014 41 42 #define FAIL_ADDRESS_LOW_OFF 0x020 43 #define FAIL_ADDRESS_HIGH_OFF 0x024 44 #define FAIL_CONTROL_OFF 0x028 45 #define FAIL_ID 0x02c 46 47 #define REGION_BASE_LOW_OFF 0x100 48 #define REGION_BASE_HIGH_OFF 0x104 49 #define REGION_TOP_LOW_OFF 0x108 50 #define REGION_TOP_HIGH_OFF 0x10c 51 #define REGION_ATTRIBUTES_OFF 0x110 52 #define REGION_ID_ACCESS_OFF 0x114 53 #define REGION_NUM_OFF(region) (0x20 * region) 54 55 /* ID Registers */ 56 #define PID0_OFF 0xfe0 57 #define PID1_OFF 0xfe4 58 #define PID2_OFF 0xfe8 59 #define PID3_OFF 0xfec 60 #define PID4_OFF 0xfd0 61 #define PID5_OFF 0xfd4 62 #define PID6_OFF 0xfd8 63 #define PID7_OFF 0xfdc 64 #define CID0_OFF 0xff0 65 #define CID1_OFF 0xff4 66 #define CID2_OFF 0xff8 67 #define CID3_OFF 0xffc 68 69 #define BUILD_CONFIG_NF_SHIFT 24 70 #define BUILD_CONFIG_NF_MASK 0x3 71 #define BUILD_CONFIG_AW_SHIFT 8 72 #define BUILD_CONFIG_AW_MASK 0x3f 73 #define BUILD_CONFIG_NR_SHIFT 0 74 #define BUILD_CONFIG_NR_MASK 0x1f 75 76 /* Not describing the case where regions 1 to 8 overlap */ 77 #define ACTION_RV_SHIFT 0 78 #define ACTION_RV_MASK 0x3 79 #define ACTION_RV_LOWOK 0x0 80 #define ACTION_RV_LOWERR 0x1 81 #define ACTION_RV_HIGHOK 0x2 82 #define ACTION_RV_HIGHERR 0x3 83 84 /* 85 * Number of gate keepers is implementation defined. But we know the max for 86 * this device is 4. Get implementation details from BUILD_CONFIG. 87 */ 88 #define GATE_KEEPER_OS_SHIFT 16 89 #define GATE_KEEPER_OS_MASK 0xf 90 #define GATE_KEEPER_OR_SHIFT 0 91 #define GATE_KEEPER_OR_MASK 0xf 92 #define GATE_KEEPER_FILTER_MASK 0x1 93 94 /* Speculation is enabled by default. */ 95 #define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) 96 #define SPECULATION_CTRL_READ_DISABLE (1 << 0) 97 98 /* Max number of filters allowed is 4. */ 99 #define INT_STATUS_OVERLAP_SHIFT 16 100 #define INT_STATUS_OVERLAP_MASK 0xf 101 #define INT_STATUS_OVERRUN_SHIFT 8 102 #define INT_STATUS_OVERRUN_MASK 0xf 103 #define INT_STATUS_STATUS_SHIFT 0 104 #define INT_STATUS_STATUS_MASK 0xf 105 106 #define INT_CLEAR_CLEAR_SHIFT 0 107 #define INT_CLEAR_CLEAR_MASK 0xf 108 109 #define FAIL_CONTROL_DIR_SHIFT (1 << 24) 110 #define FAIL_CONTROL_DIR_READ 0x0 111 #define FAIL_CONTROL_DIR_WRITE 0x1 112 #define FAIL_CONTROL_NS_SHIFT (1 << 21) 113 #define FAIL_CONTROL_NS_SECURE 0x0 114 #define FAIL_CONTROL_NS_NONSECURE 0x1 115 #define FAIL_CONTROL_PRIV_SHIFT (1 << 20) 116 #define FAIL_CONTROL_PRIV_PRIV 0x0 117 #define FAIL_CONTROL_PRIV_UNPRIV 0x1 118 119 /* 120 * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. 121 * Platform should provide the value on initialisation. 122 */ 123 #define FAIL_ID_VNET_SHIFT 24 124 #define FAIL_ID_VNET_MASK 0xf 125 #define FAIL_ID_ID_SHIFT 0 126 127 /* Used along with 'tzc_region_attributes_t' below */ 128 #define REG_ATTR_SEC_SHIFT 30 129 #define REG_ATTR_F_EN_SHIFT 0 130 #define REG_ATTR_F_EN_MASK 0xf 131 #define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT) 132 #define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \ 133 REG_ATTR_F_EN_SHIFT) 134 135 #define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 136 #define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 137 #define REGION_ID_ACCESS_NSAID_ID_MASK 0xf 138 139 140 /* Macros for setting Region ID access permissions based on NSAID */ 141 #define TZC_REGION_ACCESS_RD(id) \ 142 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 143 REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) 144 #define TZC_REGION_ACCESS_WR(id) \ 145 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 146 REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) 147 #define TZC_REGION_ACCESS_RDWR(id) \ 148 (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) 149 150 /* Consist of part_number_1 and part_number_0 */ 151 #define TZC400_PERIPHERAL_ID 0x0460 152 153 154 155 #ifndef __ASSEMBLY__ 156 157 #include <stdint.h> 158 159 /******************************************************************************* 160 * Function & variable prototypes 161 ******************************************************************************/ 162 163 /* 164 * What type of action is expected when an access violation occurs. 165 * The memory requested is zeroed. But we can also raise and event to 166 * let the system know it happened. 167 * We can raise an interrupt(INT) and/or cause an exception(ERR). 168 * TZC_ACTION_NONE - No interrupt, no Exception 169 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 170 * data abort 171 * TZC_ACTION_INT - Raise interrupt, no exception 172 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 173 * external data abort 174 */ 175 typedef enum { 176 TZC_ACTION_NONE = 0, 177 TZC_ACTION_ERR = 1, 178 TZC_ACTION_INT = 2, 179 TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) 180 } tzc_action_t; 181 182 /* 183 * Controls secure access to a region. If not enabled secure access is not 184 * allowed to region. 185 */ 186 typedef enum { 187 TZC_REGION_S_NONE = 0, 188 TZC_REGION_S_RD = 1, 189 TZC_REGION_S_WR = 2, 190 TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) 191 } tzc_region_attributes_t; 192 193 194 void tzc_init(uintptr_t base); 195 void tzc_configure_region0(tzc_region_attributes_t sec_attr, 196 uint32_t ns_device_access); 197 void tzc_configure_region(uint32_t filters, 198 uint8_t region, 199 uint64_t region_base, 200 uint64_t region_top, 201 tzc_region_attributes_t sec_attr, 202 uint32_t ns_device_access); 203 void tzc_enable_filters(void); 204 void tzc_disable_filters(void); 205 void tzc_set_action(tzc_action_t action); 206 207 #endif /* __ASSEMBLY__ */ 208 209 #endif /* __TZC400__ */ 210