xref: /rk3399_ARM-atf/include/drivers/arm/tzc400.h (revision af6491f85cc91df2349d805ceda69c0a1ab31972)
14ecca339SDan Handley /*
2dc6aad2eSRoberto Vargas  * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
34ecca339SDan Handley  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
54ecca339SDan Handley  */
64ecca339SDan Handley 
7*af6491f8SAntonio Nino Diaz #ifndef TZC400_H
8*af6491f8SAntonio Nino Diaz #define TZC400_H
94ecca339SDan Handley 
106b477063SVikram Kanigiri #include <tzc_common.h>
11*af6491f8SAntonio Nino Diaz #include <utils_def.h>
124ecca339SDan Handley 
13*af6491f8SAntonio Nino Diaz #define BUILD_CONFIG_OFF			U(0x000)
14*af6491f8SAntonio Nino Diaz #define GATE_KEEPER_OFF				U(0x008)
15*af6491f8SAntonio Nino Diaz #define SPECULATION_CTRL_OFF			U(0x00c)
16*af6491f8SAntonio Nino Diaz #define INT_STATUS				U(0x010)
17*af6491f8SAntonio Nino Diaz #define INT_CLEAR				U(0x014)
184ecca339SDan Handley 
19*af6491f8SAntonio Nino Diaz #define FAIL_ADDRESS_LOW_OFF			U(0x020)
20*af6491f8SAntonio Nino Diaz #define FAIL_ADDRESS_HIGH_OFF			U(0x024)
21*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_OFF			U(0x028)
22*af6491f8SAntonio Nino Diaz #define FAIL_ID					U(0x02c)
234ecca339SDan Handley 
246b477063SVikram Kanigiri /* ID registers not common across different varieties of TZC */
25*af6491f8SAntonio Nino Diaz #define PID5					U(0xFD4)
26*af6491f8SAntonio Nino Diaz #define PID6					U(0xFD8)
27*af6491f8SAntonio Nino Diaz #define PID7					U(0xFDC)
284ecca339SDan Handley 
294ecca339SDan Handley #define BUILD_CONFIG_NF_SHIFT			24
30*af6491f8SAntonio Nino Diaz #define BUILD_CONFIG_NF_MASK			U(0x3)
314ecca339SDan Handley #define BUILD_CONFIG_AW_SHIFT			8
32*af6491f8SAntonio Nino Diaz #define BUILD_CONFIG_AW_MASK			U(0x3f)
334ecca339SDan Handley #define BUILD_CONFIG_NR_SHIFT			0
34*af6491f8SAntonio Nino Diaz #define BUILD_CONFIG_NR_MASK			U(0x1f)
354ecca339SDan Handley 
364ecca339SDan Handley /*
374ecca339SDan Handley  * Number of gate keepers is implementation defined. But we know the max for
384ecca339SDan Handley  * this device is 4. Get implementation details from BUILD_CONFIG.
394ecca339SDan Handley  */
404ecca339SDan Handley #define GATE_KEEPER_OS_SHIFT			16
41*af6491f8SAntonio Nino Diaz #define GATE_KEEPER_OS_MASK			U(0xf)
424ecca339SDan Handley #define GATE_KEEPER_OR_SHIFT			0
43*af6491f8SAntonio Nino Diaz #define GATE_KEEPER_OR_MASK			U(0xf)
44*af6491f8SAntonio Nino Diaz #define GATE_KEEPER_FILTER_MASK			U(0x1)
454ecca339SDan Handley 
464ecca339SDan Handley /* Speculation is enabled by default. */
47*af6491f8SAntonio Nino Diaz #define SPECULATION_CTRL_WRITE_DISABLE		BIT_32(1)
48*af6491f8SAntonio Nino Diaz #define SPECULATION_CTRL_READ_DISABLE		BIT_32(0)
494ecca339SDan Handley 
504ecca339SDan Handley /* Max number of filters allowed is 4. */
514ecca339SDan Handley #define INT_STATUS_OVERLAP_SHIFT		16
52*af6491f8SAntonio Nino Diaz #define INT_STATUS_OVERLAP_MASK			U(0xf)
534ecca339SDan Handley #define INT_STATUS_OVERRUN_SHIFT		8
54*af6491f8SAntonio Nino Diaz #define INT_STATUS_OVERRUN_MASK			U(0xf)
554ecca339SDan Handley #define INT_STATUS_STATUS_SHIFT			0
56*af6491f8SAntonio Nino Diaz #define INT_STATUS_STATUS_MASK			U(0xf)
574ecca339SDan Handley 
584ecca339SDan Handley #define INT_CLEAR_CLEAR_SHIFT			0
59*af6491f8SAntonio Nino Diaz #define INT_CLEAR_CLEAR_MASK			U(0xf)
604ecca339SDan Handley 
61*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_DIR_SHIFT			24
62*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_DIR_READ			U(0)
63*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_DIR_WRITE			U(1)
64*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_NS_SHIFT			21
65*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_NS_SECURE			U(0)
66*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_NS_NONSECURE		U(1)
67*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_PRIV_SHIFT			20
68*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_PRIV_PRIV			U(0)
69*af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_PRIV_UNPRIV		U(1)
704ecca339SDan Handley 
714ecca339SDan Handley /*
724ecca339SDan Handley  * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
734ecca339SDan Handley  * Platform should provide the value on initialisation.
744ecca339SDan Handley  */
754ecca339SDan Handley #define FAIL_ID_VNET_SHIFT			24
76*af6491f8SAntonio Nino Diaz #define FAIL_ID_VNET_MASK			U(0xf)
774ecca339SDan Handley #define FAIL_ID_ID_SHIFT			0
784ecca339SDan Handley 
79*af6491f8SAntonio Nino Diaz #define TZC_400_PERIPHERAL_ID			U(0x460)
804ecca339SDan Handley 
816b477063SVikram Kanigiri /* Filter enable bits in a TZC */
82*af6491f8SAntonio Nino Diaz #define TZC_400_REGION_ATTR_F_EN_MASK		U(0xf)
83*af6491f8SAntonio Nino Diaz #define TZC_400_REGION_ATTR_FILTER_BIT(x)				\
84*af6491f8SAntonio Nino Diaz 				((U(1) << (x)) << TZC_REGION_ATTR_F_EN_SHIFT)
856b477063SVikram Kanigiri #define TZC_400_REGION_ATTR_FILTER_BIT_ALL				\
866b477063SVikram Kanigiri 				(TZC_400_REGION_ATTR_F_EN_MASK <<	\
876b477063SVikram Kanigiri 				TZC_REGION_ATTR_F_EN_SHIFT)
884ecca339SDan Handley 
896b477063SVikram Kanigiri /*
906b477063SVikram Kanigiri  * All TZC region configuration registers are placed one after another. It
916b477063SVikram Kanigiri  * depicts size of block of registers for programming each region.
926b477063SVikram Kanigiri  */
93*af6491f8SAntonio Nino Diaz #define TZC_400_REGION_SIZE			U(0x20)
94*af6491f8SAntonio Nino Diaz #define TZC_400_ACTION_OFF			U(0x4)
9571a84445SDan Handley 
9671a84445SDan Handley #ifndef __ASSEMBLY__
9771a84445SDan Handley 
986b477063SVikram Kanigiri #include <cdefs.h>
9971a84445SDan Handley #include <stdint.h>
10071a84445SDan Handley 
1014ecca339SDan Handley /*******************************************************************************
1024ecca339SDan Handley  * Function & variable prototypes
1034ecca339SDan Handley  ******************************************************************************/
1046b477063SVikram Kanigiri void tzc400_init(uintptr_t base);
105*af6491f8SAntonio Nino Diaz void tzc400_configure_region0(unsigned int sec_attr,
1066b477063SVikram Kanigiri 			   unsigned int ns_device_access);
1076b477063SVikram Kanigiri void tzc400_configure_region(unsigned int filters,
108*af6491f8SAntonio Nino Diaz 			  unsigned int region,
1099fbdb802SYatharth Kochar 			  unsigned long long region_base,
1109fbdb802SYatharth Kochar 			  unsigned long long region_top,
111*af6491f8SAntonio Nino Diaz 			  unsigned int sec_attr,
112dc6aad2eSRoberto Vargas 			  unsigned int nsaid_permissions);
113*af6491f8SAntonio Nino Diaz void tzc400_set_action(unsigned int action);
1146b477063SVikram Kanigiri void tzc400_enable_filters(void);
1156b477063SVikram Kanigiri void tzc400_disable_filters(void);
1166b477063SVikram Kanigiri 
1176b477063SVikram Kanigiri static inline void tzc_init(uintptr_t base)
1186b477063SVikram Kanigiri {
1196b477063SVikram Kanigiri 	tzc400_init(base);
1206b477063SVikram Kanigiri }
1216b477063SVikram Kanigiri 
1226b477063SVikram Kanigiri static inline void tzc_configure_region0(
123*af6491f8SAntonio Nino Diaz 			unsigned int sec_attr,
1246b477063SVikram Kanigiri 			unsigned int ns_device_access)
1256b477063SVikram Kanigiri {
1266b477063SVikram Kanigiri 	tzc400_configure_region0(sec_attr, ns_device_access);
1276b477063SVikram Kanigiri }
1286b477063SVikram Kanigiri 
1296b477063SVikram Kanigiri static inline void tzc_configure_region(
1306b477063SVikram Kanigiri 			  unsigned int filters,
131*af6491f8SAntonio Nino Diaz 			  unsigned int region,
1329fbdb802SYatharth Kochar 			  unsigned long long region_base,
1339fbdb802SYatharth Kochar 			  unsigned long long region_top,
134*af6491f8SAntonio Nino Diaz 			  unsigned int sec_attr,
1356b477063SVikram Kanigiri 			  unsigned int ns_device_access)
1366b477063SVikram Kanigiri {
1376b477063SVikram Kanigiri 	tzc400_configure_region(filters, region, region_base,
1386b477063SVikram Kanigiri 			region_top, sec_attr, ns_device_access);
1396b477063SVikram Kanigiri }
1406b477063SVikram Kanigiri 
141*af6491f8SAntonio Nino Diaz static inline void tzc_set_action(unsigned int action)
1426b477063SVikram Kanigiri {
1436b477063SVikram Kanigiri 	tzc400_set_action(action);
1446b477063SVikram Kanigiri }
1456b477063SVikram Kanigiri 
1466b477063SVikram Kanigiri 
1476b477063SVikram Kanigiri static inline void tzc_enable_filters(void)
1486b477063SVikram Kanigiri {
1496b477063SVikram Kanigiri 	tzc400_enable_filters();
1506b477063SVikram Kanigiri }
1516b477063SVikram Kanigiri 
1526b477063SVikram Kanigiri static inline void tzc_disable_filters(void)
1536b477063SVikram Kanigiri {
1546b477063SVikram Kanigiri 	tzc400_disable_filters();
1556b477063SVikram Kanigiri }
1564ecca339SDan Handley 
15771a84445SDan Handley #endif /* __ASSEMBLY__ */
1584ecca339SDan Handley 
159*af6491f8SAntonio Nino Diaz #endif /* TZC400_H */
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