14ecca339SDan Handley /* 23d66ca6dSHeyi Guo * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 34ecca339SDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 54ecca339SDan Handley */ 64ecca339SDan Handley 7af6491f8SAntonio Nino Diaz #ifndef TZC400_H 8af6491f8SAntonio Nino Diaz #define TZC400_H 94ecca339SDan Handley 1009d40e0eSAntonio Nino Diaz #include <drivers/arm/tzc_common.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 124ecca339SDan Handley 13af6491f8SAntonio Nino Diaz #define BUILD_CONFIG_OFF U(0x000) 14af6491f8SAntonio Nino Diaz #define GATE_KEEPER_OFF U(0x008) 15af6491f8SAntonio Nino Diaz #define SPECULATION_CTRL_OFF U(0x00c) 16af6491f8SAntonio Nino Diaz #define INT_STATUS U(0x010) 17af6491f8SAntonio Nino Diaz #define INT_CLEAR U(0x014) 184ecca339SDan Handley 19af6491f8SAntonio Nino Diaz #define FAIL_ADDRESS_LOW_OFF U(0x020) 20af6491f8SAntonio Nino Diaz #define FAIL_ADDRESS_HIGH_OFF U(0x024) 21af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_OFF U(0x028) 22af6491f8SAntonio Nino Diaz #define FAIL_ID U(0x02c) 234ecca339SDan Handley 246b477063SVikram Kanigiri /* ID registers not common across different varieties of TZC */ 25af6491f8SAntonio Nino Diaz #define PID5 U(0xFD4) 26af6491f8SAntonio Nino Diaz #define PID6 U(0xFD8) 27af6491f8SAntonio Nino Diaz #define PID7 U(0xFDC) 284ecca339SDan Handley 294ecca339SDan Handley #define BUILD_CONFIG_NF_SHIFT 24 30af6491f8SAntonio Nino Diaz #define BUILD_CONFIG_NF_MASK U(0x3) 314ecca339SDan Handley #define BUILD_CONFIG_AW_SHIFT 8 32af6491f8SAntonio Nino Diaz #define BUILD_CONFIG_AW_MASK U(0x3f) 334ecca339SDan Handley #define BUILD_CONFIG_NR_SHIFT 0 34af6491f8SAntonio Nino Diaz #define BUILD_CONFIG_NR_MASK U(0x1f) 354ecca339SDan Handley 364ecca339SDan Handley /* 374ecca339SDan Handley * Number of gate keepers is implementation defined. But we know the max for 384ecca339SDan Handley * this device is 4. Get implementation details from BUILD_CONFIG. 394ecca339SDan Handley */ 404ecca339SDan Handley #define GATE_KEEPER_OS_SHIFT 16 41af6491f8SAntonio Nino Diaz #define GATE_KEEPER_OS_MASK U(0xf) 424ecca339SDan Handley #define GATE_KEEPER_OR_SHIFT 0 43af6491f8SAntonio Nino Diaz #define GATE_KEEPER_OR_MASK U(0xf) 44af6491f8SAntonio Nino Diaz #define GATE_KEEPER_FILTER_MASK U(0x1) 454ecca339SDan Handley 464ecca339SDan Handley /* Speculation is enabled by default. */ 47af6491f8SAntonio Nino Diaz #define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1) 48af6491f8SAntonio Nino Diaz #define SPECULATION_CTRL_READ_DISABLE BIT_32(0) 494ecca339SDan Handley 504ecca339SDan Handley /* Max number of filters allowed is 4. */ 514ecca339SDan Handley #define INT_STATUS_OVERLAP_SHIFT 16 52af6491f8SAntonio Nino Diaz #define INT_STATUS_OVERLAP_MASK U(0xf) 534ecca339SDan Handley #define INT_STATUS_OVERRUN_SHIFT 8 54af6491f8SAntonio Nino Diaz #define INT_STATUS_OVERRUN_MASK U(0xf) 554ecca339SDan Handley #define INT_STATUS_STATUS_SHIFT 0 56af6491f8SAntonio Nino Diaz #define INT_STATUS_STATUS_MASK U(0xf) 574ecca339SDan Handley 584ecca339SDan Handley #define INT_CLEAR_CLEAR_SHIFT 0 59af6491f8SAntonio Nino Diaz #define INT_CLEAR_CLEAR_MASK U(0xf) 604ecca339SDan Handley 61af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_DIR_SHIFT 24 62af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_DIR_READ U(0) 63af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_DIR_WRITE U(1) 64af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_NS_SHIFT 21 65af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_NS_SECURE U(0) 66af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_NS_NONSECURE U(1) 67af6491f8SAntonio Nino Diaz #define FAIL_CONTROL_PRIV_SHIFT 20 684f81ed8eSYann Gautier #define FAIL_CONTROL_PRIV_UNPRIV U(0) 694f81ed8eSYann Gautier #define FAIL_CONTROL_PRIV_PRIV U(1) 704ecca339SDan Handley 714ecca339SDan Handley /* 724ecca339SDan Handley * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. 734ecca339SDan Handley * Platform should provide the value on initialisation. 744ecca339SDan Handley */ 754ecca339SDan Handley #define FAIL_ID_VNET_SHIFT 24 76af6491f8SAntonio Nino Diaz #define FAIL_ID_VNET_MASK U(0xf) 774ecca339SDan Handley #define FAIL_ID_ID_SHIFT 0 784ecca339SDan Handley 79af6491f8SAntonio Nino Diaz #define TZC_400_PERIPHERAL_ID U(0x460) 804ecca339SDan Handley 816b477063SVikram Kanigiri /* Filter enable bits in a TZC */ 82af6491f8SAntonio Nino Diaz #define TZC_400_REGION_ATTR_F_EN_MASK U(0xf) 833d66ca6dSHeyi Guo #define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x)) 843d66ca6dSHeyi Guo #define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK 854ecca339SDan Handley 866b477063SVikram Kanigiri /* 876b477063SVikram Kanigiri * All TZC region configuration registers are placed one after another. It 886b477063SVikram Kanigiri * depicts size of block of registers for programming each region. 896b477063SVikram Kanigiri */ 90af6491f8SAntonio Nino Diaz #define TZC_400_REGION_SIZE U(0x20) 91af6491f8SAntonio Nino Diaz #define TZC_400_ACTION_OFF U(0x4) 9271a84445SDan Handley 93*34c1a1a4SYann Gautier #define FILTER_OFFSET U(0x10) 94*34c1a1a4SYann Gautier 95d5dfdeb6SJulius Werner #ifndef __ASSEMBLER__ 9671a84445SDan Handley 976b477063SVikram Kanigiri #include <cdefs.h> 9871a84445SDan Handley #include <stdint.h> 9971a84445SDan Handley 1004ecca339SDan Handley /******************************************************************************* 1014ecca339SDan Handley * Function & variable prototypes 1024ecca339SDan Handley ******************************************************************************/ 1036b477063SVikram Kanigiri void tzc400_init(uintptr_t base); 104af6491f8SAntonio Nino Diaz void tzc400_configure_region0(unsigned int sec_attr, 1056b477063SVikram Kanigiri unsigned int ns_device_access); 1066b477063SVikram Kanigiri void tzc400_configure_region(unsigned int filters, 107af6491f8SAntonio Nino Diaz unsigned int region, 1089fbdb802SYatharth Kochar unsigned long long region_base, 1099fbdb802SYatharth Kochar unsigned long long region_top, 110af6491f8SAntonio Nino Diaz unsigned int sec_attr, 111dc6aad2eSRoberto Vargas unsigned int nsaid_permissions); 112af6491f8SAntonio Nino Diaz void tzc400_set_action(unsigned int action); 1136b477063SVikram Kanigiri void tzc400_enable_filters(void); 1146b477063SVikram Kanigiri void tzc400_disable_filters(void); 115*34c1a1a4SYann Gautier int tzc400_it_handler(void); 1166b477063SVikram Kanigiri 1176b477063SVikram Kanigiri static inline void tzc_init(uintptr_t base) 1186b477063SVikram Kanigiri { 1196b477063SVikram Kanigiri tzc400_init(base); 1206b477063SVikram Kanigiri } 1216b477063SVikram Kanigiri 1226b477063SVikram Kanigiri static inline void tzc_configure_region0( 123af6491f8SAntonio Nino Diaz unsigned int sec_attr, 1246b477063SVikram Kanigiri unsigned int ns_device_access) 1256b477063SVikram Kanigiri { 1266b477063SVikram Kanigiri tzc400_configure_region0(sec_attr, ns_device_access); 1276b477063SVikram Kanigiri } 1286b477063SVikram Kanigiri 1296b477063SVikram Kanigiri static inline void tzc_configure_region( 1306b477063SVikram Kanigiri unsigned int filters, 131af6491f8SAntonio Nino Diaz unsigned int region, 1329fbdb802SYatharth Kochar unsigned long long region_base, 1339fbdb802SYatharth Kochar unsigned long long region_top, 134af6491f8SAntonio Nino Diaz unsigned int sec_attr, 1356b477063SVikram Kanigiri unsigned int ns_device_access) 1366b477063SVikram Kanigiri { 1376b477063SVikram Kanigiri tzc400_configure_region(filters, region, region_base, 1386b477063SVikram Kanigiri region_top, sec_attr, ns_device_access); 1396b477063SVikram Kanigiri } 1406b477063SVikram Kanigiri 141af6491f8SAntonio Nino Diaz static inline void tzc_set_action(unsigned int action) 1426b477063SVikram Kanigiri { 1436b477063SVikram Kanigiri tzc400_set_action(action); 1446b477063SVikram Kanigiri } 1456b477063SVikram Kanigiri 1466b477063SVikram Kanigiri 1476b477063SVikram Kanigiri static inline void tzc_enable_filters(void) 1486b477063SVikram Kanigiri { 1496b477063SVikram Kanigiri tzc400_enable_filters(); 1506b477063SVikram Kanigiri } 1516b477063SVikram Kanigiri 1526b477063SVikram Kanigiri static inline void tzc_disable_filters(void) 1536b477063SVikram Kanigiri { 1546b477063SVikram Kanigiri tzc400_disable_filters(); 1556b477063SVikram Kanigiri } 1564ecca339SDan Handley 157d5dfdeb6SJulius Werner #endif /* __ASSEMBLER__ */ 1584ecca339SDan Handley 159af6491f8SAntonio Nino Diaz #endif /* TZC400_H */ 160