11154586bSJeenu Viswambharan /* 2*6d5f0631SAntonio Nino Diaz * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 31154586bSJeenu Viswambharan * 41154586bSJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 51154586bSJeenu Viswambharan */ 61154586bSJeenu Viswambharan 71154586bSJeenu Viswambharan #ifndef __SMMU_V3_H__ 81154586bSJeenu Viswambharan #define __SMMU_V3_H__ 91154586bSJeenu Viswambharan 10*6d5f0631SAntonio Nino Diaz #include <utils_def.h> 111154586bSJeenu Viswambharan #include <stdint.h> 121154586bSJeenu Viswambharan 131154586bSJeenu Viswambharan /* SMMUv3 register offsets from device base */ 14*6d5f0631SAntonio Nino Diaz #define SMMU_S_IDR1 U(0x8004) 15*6d5f0631SAntonio Nino Diaz #define SMMU_S_INIT U(0x803c) 161154586bSJeenu Viswambharan 171154586bSJeenu Viswambharan /* SMMU_S_IDR1 register fields */ 181154586bSJeenu Viswambharan #define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31 19*6d5f0631SAntonio Nino Diaz #define SMMU_S_IDR1_SECURE_IMPL_MASK U(0x1) 201154586bSJeenu Viswambharan 211154586bSJeenu Viswambharan /* SMMU_S_INIT register fields */ 22*6d5f0631SAntonio Nino Diaz #define SMMU_S_INIT_INV_ALL_MASK U(0x1) 231154586bSJeenu Viswambharan 241154586bSJeenu Viswambharan 251154586bSJeenu Viswambharan int smmuv3_init(uintptr_t smmu_base); 261154586bSJeenu Viswambharan 271154586bSJeenu Viswambharan #endif /* __SMMU_V3_H__ */ 28