11154586bSJeenu Viswambharan /* 2*52a314afSOlivier Deprez * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 31154586bSJeenu Viswambharan * 41154586bSJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 51154586bSJeenu Viswambharan */ 61154586bSJeenu Viswambharan 7c3cf06f1SAntonio Nino Diaz #ifndef SMMU_V3_H 8c3cf06f1SAntonio Nino Diaz #define SMMU_V3_H 91154586bSJeenu Viswambharan 101154586bSJeenu Viswambharan #include <stdint.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 12*52a314afSOlivier Deprez #include <platform_def.h> 131154586bSJeenu Viswambharan 141154586bSJeenu Viswambharan /* SMMUv3 register offsets from device base */ 15ccd4d475SAlexei Fedorov #define SMMU_GBPA U(0x0044) 166d5f0631SAntonio Nino Diaz #define SMMU_S_IDR1 U(0x8004) 176d5f0631SAntonio Nino Diaz #define SMMU_S_INIT U(0x803c) 18ccd4d475SAlexei Fedorov #define SMMU_S_GBPA U(0x8044) 19ccd4d475SAlexei Fedorov 20*52a314afSOlivier Deprez /* 21*52a314afSOlivier Deprez * TODO: SMMU_ROOT_PAGE_OFFSET is platform specific. 22*52a314afSOlivier Deprez * Currently defined as a command line model parameter. 23*52a314afSOlivier Deprez */ 24*52a314afSOlivier Deprez #if ENABLE_RME 25*52a314afSOlivier Deprez 26*52a314afSOlivier Deprez #define SMMU_ROOT_PAGE_OFFSET (PLAT_ARM_SMMUV3_ROOT_REG_OFFSET) 27*52a314afSOlivier Deprez #define SMMU_ROOT_IDR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0000) 28*52a314afSOlivier Deprez #define SMMU_ROOT_IIDR U(SMMU_ROOT_PAGE_OFFSET + 0x0008) 29*52a314afSOlivier Deprez #define SMMU_ROOT_CR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0020) 30*52a314afSOlivier Deprez #define SMMU_ROOT_CR0ACK U(SMMU_ROOT_PAGE_OFFSET + 0x0024) 31*52a314afSOlivier Deprez #define SMMU_ROOT_GPT_BASE U(SMMU_ROOT_PAGE_OFFSET + 0x0028) 32*52a314afSOlivier Deprez #define SMMU_ROOT_GPT_BASE_CFG U(SMMU_ROOT_PAGE_OFFSET + 0x0030) 33*52a314afSOlivier Deprez #define SMMU_ROOT_GPF_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0038) 34*52a314afSOlivier Deprez #define SMMU_ROOT_GPT_CFG_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0040) 35*52a314afSOlivier Deprez #define SMMU_ROOT_TLBI U(SMMU_ROOT_PAGE_OFFSET + 0x0050) 36*52a314afSOlivier Deprez #define SMMU_ROOT_TLBI_CTRL U(SMMU_ROOT_PAGE_OFFSET + 0x0058) 37*52a314afSOlivier Deprez 38*52a314afSOlivier Deprez #endif /* ENABLE_RME */ 39*52a314afSOlivier Deprez 40ccd4d475SAlexei Fedorov /* SMMU_GBPA register fields */ 41ccd4d475SAlexei Fedorov #define SMMU_GBPA_UPDATE (1UL << 31) 42ccd4d475SAlexei Fedorov #define SMMU_GBPA_ABORT (1UL << 20) 431154586bSJeenu Viswambharan 441154586bSJeenu Viswambharan /* SMMU_S_IDR1 register fields */ 45ccd4d475SAlexei Fedorov #define SMMU_S_IDR1_SECURE_IMPL (1UL << 31) 461154586bSJeenu Viswambharan 471154586bSJeenu Viswambharan /* SMMU_S_INIT register fields */ 48ccd4d475SAlexei Fedorov #define SMMU_S_INIT_INV_ALL (1UL << 0) 491154586bSJeenu Viswambharan 50ccd4d475SAlexei Fedorov /* SMMU_S_GBPA register fields */ 51ccd4d475SAlexei Fedorov #define SMMU_S_GBPA_UPDATE (1UL << 31) 52ccd4d475SAlexei Fedorov #define SMMU_S_GBPA_ABORT (1UL << 20) 531154586bSJeenu Viswambharan 54*52a314afSOlivier Deprez /* SMMU_ROOT_IDR0 register fields */ 55*52a314afSOlivier Deprez #define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0) 56*52a314afSOlivier Deprez 57*52a314afSOlivier Deprez /* SMMU_ROOT_CR0 register fields */ 58*52a314afSOlivier Deprez #define SMMU_ROOT_CR0_GPCEN (1UL << 1) 59*52a314afSOlivier Deprez #define SMMU_ROOT_CR0_ACCESSEN (1UL << 0) 60*52a314afSOlivier Deprez 611154586bSJeenu Viswambharan int smmuv3_init(uintptr_t smmu_base); 621461ad9fSAlexei Fedorov int smmuv3_security_init(uintptr_t smmu_base); 631154586bSJeenu Viswambharan 64c3cf06f1SAntonio Nino Diaz #endif /* SMMU_V3_H */ 65