11154586bSJeenu Viswambharan /* 2ccd4d475SAlexei Fedorov * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 31154586bSJeenu Viswambharan * 41154586bSJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 51154586bSJeenu Viswambharan */ 61154586bSJeenu Viswambharan 7c3cf06f1SAntonio Nino Diaz #ifndef SMMU_V3_H 8c3cf06f1SAntonio Nino Diaz #define SMMU_V3_H 91154586bSJeenu Viswambharan 101154586bSJeenu Viswambharan #include <stdint.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 121154586bSJeenu Viswambharan 131154586bSJeenu Viswambharan /* SMMUv3 register offsets from device base */ 14ccd4d475SAlexei Fedorov #define SMMU_GBPA U(0x0044) 156d5f0631SAntonio Nino Diaz #define SMMU_S_IDR1 U(0x8004) 166d5f0631SAntonio Nino Diaz #define SMMU_S_INIT U(0x803c) 17ccd4d475SAlexei Fedorov #define SMMU_S_GBPA U(0x8044) 18ccd4d475SAlexei Fedorov 19ccd4d475SAlexei Fedorov /* SMMU_GBPA register fields */ 20ccd4d475SAlexei Fedorov #define SMMU_GBPA_UPDATE (1UL << 31) 21ccd4d475SAlexei Fedorov #define SMMU_GBPA_ABORT (1UL << 20) 221154586bSJeenu Viswambharan 231154586bSJeenu Viswambharan /* SMMU_S_IDR1 register fields */ 24ccd4d475SAlexei Fedorov #define SMMU_S_IDR1_SECURE_IMPL (1UL << 31) 251154586bSJeenu Viswambharan 261154586bSJeenu Viswambharan /* SMMU_S_INIT register fields */ 27ccd4d475SAlexei Fedorov #define SMMU_S_INIT_INV_ALL (1UL << 0) 281154586bSJeenu Viswambharan 29ccd4d475SAlexei Fedorov /* SMMU_S_GBPA register fields */ 30ccd4d475SAlexei Fedorov #define SMMU_S_GBPA_UPDATE (1UL << 31) 31ccd4d475SAlexei Fedorov #define SMMU_S_GBPA_ABORT (1UL << 20) 321154586bSJeenu Viswambharan 331154586bSJeenu Viswambharan int smmuv3_init(uintptr_t smmu_base); 34*1461ad9fSAlexei Fedorov int smmuv3_security_init(uintptr_t smmu_base); 351154586bSJeenu Viswambharan 36c3cf06f1SAntonio Nino Diaz #endif /* SMMU_V3_H */ 37