1*1154586bSJeenu Viswambharan /* 2*1154586bSJeenu Viswambharan * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*1154586bSJeenu Viswambharan * 4*1154586bSJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 5*1154586bSJeenu Viswambharan */ 6*1154586bSJeenu Viswambharan 7*1154586bSJeenu Viswambharan #ifndef __SMMU_V3_H__ 8*1154586bSJeenu Viswambharan #define __SMMU_V3_H__ 9*1154586bSJeenu Viswambharan 10*1154586bSJeenu Viswambharan #include <stdint.h> 11*1154586bSJeenu Viswambharan 12*1154586bSJeenu Viswambharan /* SMMUv3 register offsets from device base */ 13*1154586bSJeenu Viswambharan #define SMMU_S_IDR1 0x8004 14*1154586bSJeenu Viswambharan #define SMMU_S_INIT 0x803c 15*1154586bSJeenu Viswambharan 16*1154586bSJeenu Viswambharan /* SMMU_S_IDR1 register fields */ 17*1154586bSJeenu Viswambharan #define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31 18*1154586bSJeenu Viswambharan #define SMMU_S_IDR1_SECURE_IMPL_MASK 0x1 19*1154586bSJeenu Viswambharan 20*1154586bSJeenu Viswambharan /* SMMU_S_INIT register fields */ 21*1154586bSJeenu Viswambharan #define SMMU_S_INIT_INV_ALL_MASK 0x1 22*1154586bSJeenu Viswambharan 23*1154586bSJeenu Viswambharan 24*1154586bSJeenu Viswambharan int smmuv3_init(uintptr_t smmu_base); 25*1154586bSJeenu Viswambharan 26*1154586bSJeenu Viswambharan #endif /* __SMMU_V3_H__ */ 27