xref: /rk3399_ARM-atf/include/drivers/arm/gicv5.h (revision 82b228ba638cb027cbedfbd4835587b6c465fedc)
18cef63d6SBoyan Karatotev /*
28cef63d6SBoyan Karatotev  * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
38cef63d6SBoyan Karatotev  *
48cef63d6SBoyan Karatotev  * SPDX-License-Identifier: BSD-3-Clause
58cef63d6SBoyan Karatotev  */
68cef63d6SBoyan Karatotev 
78cef63d6SBoyan Karatotev #ifndef GICV5_H
88cef63d6SBoyan Karatotev #define GICV5_H
913b62814SBoyan Karatotev 
1013b62814SBoyan Karatotev #ifndef __ASSEMBLER__
1113b62814SBoyan Karatotev #include <stdbool.h>
1213b62814SBoyan Karatotev #include <stdint.h>
1313b62814SBoyan Karatotev #endif
1413b62814SBoyan Karatotev 
1513b62814SBoyan Karatotev #include <lib/utils_def.h>
1613b62814SBoyan Karatotev 
1713b62814SBoyan Karatotev /* Interrupt Domain definitions */
1813b62814SBoyan Karatotev #define INTDMN_S				0
1913b62814SBoyan Karatotev #define INTDMN_NS				1
2013b62814SBoyan Karatotev #define INTDMN_EL3				2
2113b62814SBoyan Karatotev #define INTDMN_RL				3
2213b62814SBoyan Karatotev 
2313b62814SBoyan Karatotev /* Trigger modes */
2413b62814SBoyan Karatotev #define TM_EDGE					0
2513b62814SBoyan Karatotev #define TM_LEVEL				1
2613b62814SBoyan Karatotev 
27*82b228baSBoyan Karatotev /* Architected PPI numbers */
28*82b228baSBoyan Karatotev #define PPI_TRBIRQ				31
29*82b228baSBoyan Karatotev #define PPI_CNTP				30
30*82b228baSBoyan Karatotev #define PPI_CNTPS				29
31*82b228baSBoyan Karatotev #define PPI_CNTHV				28
32*82b228baSBoyan Karatotev #define PPI_CNTV				27
33*82b228baSBoyan Karatotev #define PPI_CNTHP				26
34*82b228baSBoyan Karatotev #define PPI_GICMNT				25
35*82b228baSBoyan Karatotev #define PPI_CTIIRQ				24
36*82b228baSBoyan Karatotev #define PPI_PMUIRQ				23
37*82b228baSBoyan Karatotev #define PPI_COMMIRQ				22
38*82b228baSBoyan Karatotev #define PPI_PMBIRQ				21
39*82b228baSBoyan Karatotev #define PPI_CNTHPS				20
40*82b228baSBoyan Karatotev #define PPI_CNTHVS				19
41*82b228baSBoyan Karatotev #define PPI_DB_NS				2
42*82b228baSBoyan Karatotev #define PPI_DB_RL				1
43*82b228baSBoyan Karatotev #define PPI_DB_S				0
44*82b228baSBoyan Karatotev 
4513b62814SBoyan Karatotev #ifndef __ASSEMBLER__
4613b62814SBoyan Karatotev 
47*82b228baSBoyan Karatotev #define _PPI_FIELD_SHIFT(_REG, _ppi_id)						\
48*82b228baSBoyan Karatotev 	((_ppi_id % (ICC_PPI_##_REG##_COUNT)) * (64 / ICC_PPI_##_REG##_COUNT))
49*82b228baSBoyan Karatotev 
50*82b228baSBoyan Karatotev #define write_icc_ppi_domainr(_var, _ppi_id, _value)				\
51*82b228baSBoyan Karatotev 	do {									\
52*82b228baSBoyan Karatotev 		_var |=  (uint64_t)_value << _PPI_FIELD_SHIFT(DOMAINR, _ppi_id);\
53*82b228baSBoyan Karatotev 	} while (false)
54*82b228baSBoyan Karatotev 
5513b62814SBoyan Karatotev struct gicv5_driver_data {
5613b62814SBoyan Karatotev };
5713b62814SBoyan Karatotev 
5813b62814SBoyan Karatotev extern const struct gicv5_driver_data plat_gicv5_driver_data;
5913b62814SBoyan Karatotev 
6013b62814SBoyan Karatotev void gicv5_driver_init();
6113b62814SBoyan Karatotev uint8_t gicv5_get_pending_interrupt_type(void);
6213b62814SBoyan Karatotev bool gicv5_has_interrupt_type(unsigned int type);
63*82b228baSBoyan Karatotev void gicv5_enable_ppis();
6413b62814SBoyan Karatotev #endif /* __ASSEMBLER__ */
658cef63d6SBoyan Karatotev #endif /* GICV5_H */
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