1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV3_H 8 #define GICV3_H 9 10 /******************************************************************************* 11 * GICv3 miscellaneous definitions 12 ******************************************************************************/ 13 /* Interrupt group definitions */ 14 #define INTR_GROUP1S U(0) 15 #define INTR_GROUP0 U(1) 16 #define INTR_GROUP1NS U(2) 17 18 /* Interrupt IDs reported by the HPPIR and IAR registers */ 19 #define PENDING_G1S_INTID U(1020) 20 #define PENDING_G1NS_INTID U(1021) 21 22 /* Constant to categorize LPI interrupt */ 23 #define MIN_LPI_ID U(8192) 24 25 /* GICv3 can only target up to 16 PEs with SGI */ 26 #define GICV3_MAX_SGI_TARGETS U(16) 27 28 /******************************************************************************* 29 * GICv3 specific Distributor interface register offsets and constants. 30 ******************************************************************************/ 31 #define GICD_STATUSR U(0x10) 32 #define GICD_SETSPI_NSR U(0x40) 33 #define GICD_CLRSPI_NSR U(0x48) 34 #define GICD_SETSPI_SR U(0x50) 35 #define GICD_CLRSPI_SR U(0x50) 36 #define GICD_IGRPMODR U(0xd00) 37 /* 38 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and 39 * n >= 32, making the effective offset as 0x6100. 40 */ 41 #define GICD_IROUTER U(0x6000) 42 #define GICD_PIDR2_GICV3 U(0xffe8) 43 44 #define IGRPMODR_SHIFT 5 45 46 /* GICD_CTLR bit definitions */ 47 #define CTLR_ENABLE_G1NS_SHIFT 1 48 #define CTLR_ENABLE_G1S_SHIFT 2 49 #define CTLR_ARE_S_SHIFT 4 50 #define CTLR_ARE_NS_SHIFT 5 51 #define CTLR_DS_SHIFT 6 52 #define CTLR_E1NWF_SHIFT 7 53 #define GICD_CTLR_RWP_SHIFT 31 54 55 #define CTLR_ENABLE_G1NS_MASK U(0x1) 56 #define CTLR_ENABLE_G1S_MASK U(0x1) 57 #define CTLR_ARE_S_MASK U(0x1) 58 #define CTLR_ARE_NS_MASK U(0x1) 59 #define CTLR_DS_MASK U(0x1) 60 #define CTLR_E1NWF_MASK U(0x1) 61 #define GICD_CTLR_RWP_MASK U(0x1) 62 63 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT) 64 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT) 65 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT) 66 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT) 67 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT) 68 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT) 69 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT) 70 71 /* GICD_IROUTER shifts and masks */ 72 #define IROUTER_SHIFT 0 73 #define IROUTER_IRM_SHIFT 31 74 #define IROUTER_IRM_MASK U(0x1) 75 76 #define GICV3_IRM_PE U(0) 77 #define GICV3_IRM_ANY U(1) 78 79 #define NUM_OF_DIST_REGS 30 80 81 /******************************************************************************* 82 * GICv3 Re-distributor interface registers & constants 83 ******************************************************************************/ 84 #define GICR_PCPUBASE_SHIFT 0x11 85 #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */ 86 #define GICR_CTLR U(0x0) 87 #define GICR_TYPER U(0x08) 88 #define GICR_WAKER U(0x14) 89 #define GICR_PROPBASER U(0x70) 90 #define GICR_PENDBASER U(0x78) 91 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + U(0x80)) 92 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100)) 93 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + U(0x180)) 94 #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + U(0x200)) 95 #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + U(0x280)) 96 #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + U(0x300)) 97 #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + U(0x380)) 98 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + U(0x400)) 99 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + U(0xc00)) 100 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + U(0xc04)) 101 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00)) 102 #define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00)) 103 104 /* GICR_CTLR bit definitions */ 105 #define GICR_CTLR_UWP_SHIFT 31 106 #define GICR_CTLR_UWP_MASK U(0x1) 107 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT) 108 #define GICR_CTLR_RWP_SHIFT 3 109 #define GICR_CTLR_RWP_MASK U(0x1) 110 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT) 111 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0) 112 113 /* GICR_WAKER bit definitions */ 114 #define WAKER_CA_SHIFT 2 115 #define WAKER_PS_SHIFT 1 116 117 #define WAKER_CA_MASK U(0x1) 118 #define WAKER_PS_MASK U(0x1) 119 120 #define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT) 121 #define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT) 122 123 /* GICR_TYPER bit definitions */ 124 #define TYPER_AFF_VAL_SHIFT 32 125 #define TYPER_PROC_NUM_SHIFT 8 126 #define TYPER_LAST_SHIFT 4 127 128 #define TYPER_AFF_VAL_MASK U(0xffffffff) 129 #define TYPER_PROC_NUM_MASK U(0xffff) 130 #define TYPER_LAST_MASK U(0x1) 131 132 #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT) 133 134 #define NUM_OF_REDIST_REGS 30 135 136 /******************************************************************************* 137 * GICv3 CPU interface registers & constants 138 ******************************************************************************/ 139 /* ICC_SRE bit definitions*/ 140 #define ICC_SRE_EN_BIT BIT_32(3) 141 #define ICC_SRE_DIB_BIT BIT_32(2) 142 #define ICC_SRE_DFB_BIT BIT_32(1) 143 #define ICC_SRE_SRE_BIT BIT_32(0) 144 145 /* ICC_IGRPEN1_EL3 bit definitions */ 146 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 147 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 148 149 #define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT) 150 #define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT) 151 152 /* ICC_IGRPEN0_EL1 bit definitions */ 153 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 154 #define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT) 155 156 /* ICC_HPPIR0_EL1 bit definitions */ 157 #define HPPIR0_EL1_INTID_SHIFT 0 158 #define HPPIR0_EL1_INTID_MASK U(0xffffff) 159 160 /* ICC_HPPIR1_EL1 bit definitions */ 161 #define HPPIR1_EL1_INTID_SHIFT 0 162 #define HPPIR1_EL1_INTID_MASK U(0xffffff) 163 164 /* ICC_IAR0_EL1 bit definitions */ 165 #define IAR0_EL1_INTID_SHIFT 0 166 #define IAR0_EL1_INTID_MASK U(0xffffff) 167 168 /* ICC_IAR1_EL1 bit definitions */ 169 #define IAR1_EL1_INTID_SHIFT 0 170 #define IAR1_EL1_INTID_MASK U(0xffffff) 171 172 /* ICC SGI macros */ 173 #define SGIR_TGT_MASK ULL(0xffff) 174 #define SGIR_AFF1_SHIFT 16 175 #define SGIR_INTID_SHIFT 24 176 #define SGIR_INTID_MASK ULL(0xf) 177 #define SGIR_AFF2_SHIFT 32 178 #define SGIR_IRM_SHIFT 40 179 #define SGIR_IRM_MASK ULL(0x1) 180 #define SGIR_AFF3_SHIFT 48 181 #define SGIR_AFF_MASK ULL(0xf) 182 183 #define SGIR_IRM_TO_AFF U(0) 184 185 #define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \ 186 ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \ 187 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \ 188 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \ 189 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \ 190 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \ 191 ((_tgt) & SGIR_TGT_MASK)) 192 193 /***************************************************************************** 194 * GICv3 ITS registers and constants 195 *****************************************************************************/ 196 197 #define GITS_CTLR U(0x0) 198 #define GITS_IIDR U(0x4) 199 #define GITS_TYPER U(0x8) 200 #define GITS_CBASER U(0x80) 201 #define GITS_CWRITER U(0x88) 202 #define GITS_CREADR U(0x90) 203 #define GITS_BASER U(0x100) 204 205 /* GITS_CTLR bit definitions */ 206 #define GITS_CTLR_ENABLED_BIT BIT_32(0) 207 #define GITS_CTLR_QUIESCENT_SHIFT 31 208 #define GITS_CTLR_QUIESCENT_BIT BIT_32(GITS_CTLR_QUIESCENT_SHIFT) 209 210 #ifndef __ASSEMBLY__ 211 212 #include <stdbool.h> 213 #include <stdint.h> 214 215 #include <arch_helpers.h> 216 #include <common/interrupt_props.h> 217 #include <drivers/arm/gic_common.h> 218 #include <lib/utils_def.h> 219 220 static inline bool gicv3_is_intr_id_special_identifier(unsigned int id) 221 { 222 return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT); 223 } 224 225 /******************************************************************************* 226 * Helper GICv3 macros for SEL1 227 ******************************************************************************/ 228 static inline uint32_t gicv3_acknowledge_interrupt_sel1(void) 229 { 230 return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK; 231 } 232 233 static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void) 234 { 235 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 236 } 237 238 static inline void gicv3_end_of_interrupt_sel1(unsigned int id) 239 { 240 write_icc_eoir1_el1(id); 241 } 242 243 /******************************************************************************* 244 * Helper GICv3 macros for EL3 245 ******************************************************************************/ 246 static inline uint32_t gicv3_acknowledge_interrupt(void) 247 { 248 return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK; 249 } 250 251 static inline void gicv3_end_of_interrupt(unsigned int id) 252 { 253 return write_icc_eoir0_el1(id); 254 } 255 256 /* 257 * This macro returns the total number of GICD registers corresponding to 258 * the name. 259 */ 260 #define GICD_NUM_REGS(reg_name) \ 261 DIV_ROUND_UP_2EVAL(TOTAL_SPI_INTR_NUM, (1 << reg_name ## _SHIFT)) 262 263 #define GICR_NUM_REGS(reg_name) \ 264 DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT)) 265 266 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 267 #define INT_ID_MASK U(0xffffff) 268 269 /******************************************************************************* 270 * This structure describes some of the implementation defined attributes of the 271 * GICv3 IP. It is used by the platform port to specify these attributes in order 272 * to initialise the GICV3 driver. The attributes are described below. 273 * 274 * The 'gicd_base' field contains the base address of the Distributor interface 275 * programmer's view. 276 * 277 * The 'gicr_base' field contains the base address of the Re-distributor 278 * interface programmer's view. 279 * 280 * The 'interrupt_props' field is a pointer to an array that enumerates secure 281 * interrupts and their properties. If this field is not NULL, both 282 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored. 283 * 284 * The 'interrupt_props_num' field contains the number of entries in the 285 * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num' 286 * and 'g1s_interrupt_num' are ignored. 287 * 288 * The 'rdistif_num' field contains the number of Redistributor interfaces the 289 * GIC implements. This is equal to the number of CPUs or CPU interfaces 290 * instantiated in the GIC. 291 * 292 * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for 293 * storing the base address of the Redistributor interface frame of each CPU in 294 * the system. The size of the array = 'rdistif_num'. The base addresses are 295 * detected during driver initialisation. 296 * 297 * The 'mpidr_to_core_pos' field is a pointer to a hash function which the 298 * driver will use to convert an MPIDR value to a linear core index. This index 299 * will be used for accessing the 'rdistif_base_addrs' array. This is an 300 * optional field. A GICv3 implementation maps each MPIDR to a linear core index 301 * as well. This mapping can be found by reading the "Affinity Value" and 302 * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the 303 * "Processor Numbers" are suitable to index into an array to access core 304 * specific information. If this not the case, the platform port must provide a 305 * hash function. Otherwise, the "Processor Number" field will be used to access 306 * the array elements. 307 ******************************************************************************/ 308 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr); 309 310 typedef struct gicv3_driver_data { 311 uintptr_t gicd_base; 312 uintptr_t gicr_base; 313 const interrupt_prop_t *interrupt_props; 314 unsigned int interrupt_props_num; 315 unsigned int rdistif_num; 316 uintptr_t *rdistif_base_addrs; 317 mpidr_hash_fn mpidr_to_core_pos; 318 } gicv3_driver_data_t; 319 320 typedef struct gicv3_redist_ctx { 321 /* 64 bits registers */ 322 uint64_t gicr_propbaser; 323 uint64_t gicr_pendbaser; 324 325 /* 32 bits registers */ 326 uint32_t gicr_ctlr; 327 uint32_t gicr_igroupr0; 328 uint32_t gicr_isenabler0; 329 uint32_t gicr_ispendr0; 330 uint32_t gicr_isactiver0; 331 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)]; 332 uint32_t gicr_icfgr0; 333 uint32_t gicr_icfgr1; 334 uint32_t gicr_igrpmodr0; 335 uint32_t gicr_nsacr; 336 } gicv3_redist_ctx_t; 337 338 typedef struct gicv3_dist_ctx { 339 /* 64 bits registers */ 340 uint64_t gicd_irouter[TOTAL_SPI_INTR_NUM]; 341 342 /* 32 bits registers */ 343 uint32_t gicd_ctlr; 344 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)]; 345 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)]; 346 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)]; 347 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)]; 348 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)]; 349 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)]; 350 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)]; 351 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)]; 352 } gicv3_dist_ctx_t; 353 354 typedef struct gicv3_its_ctx { 355 /* 64 bits registers */ 356 uint64_t gits_cbaser; 357 uint64_t gits_cwriter; 358 uint64_t gits_baser[8]; 359 360 /* 32 bits registers */ 361 uint32_t gits_ctlr; 362 } gicv3_its_ctx_t; 363 364 /******************************************************************************* 365 * GICv3 EL3 driver API 366 ******************************************************************************/ 367 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); 368 void gicv3_distif_init(void); 369 void gicv3_rdistif_init(unsigned int proc_num); 370 void gicv3_rdistif_on(unsigned int proc_num); 371 void gicv3_rdistif_off(unsigned int proc_num); 372 void gicv3_cpuif_enable(unsigned int proc_num); 373 void gicv3_cpuif_disable(unsigned int proc_num); 374 unsigned int gicv3_get_pending_interrupt_type(void); 375 unsigned int gicv3_get_pending_interrupt_id(void); 376 unsigned int gicv3_get_interrupt_type(unsigned int id, 377 unsigned int proc_num); 378 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx); 379 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx); 380 /* 381 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if 382 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no 383 * implementation-defined sequence is needed at these steps, an empty function 384 * can be provided. 385 */ 386 void gicv3_distif_post_restore(unsigned int proc_num); 387 void gicv3_distif_pre_save(unsigned int proc_num); 388 void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx); 389 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx); 390 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx); 391 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx); 392 393 unsigned int gicv3_get_running_priority(void); 394 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num); 395 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num); 396 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num); 397 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 398 unsigned int priority); 399 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 400 unsigned int type); 401 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target); 402 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, 403 u_register_t mpidr); 404 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num); 405 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num); 406 unsigned int gicv3_set_pmr(unsigned int mask); 407 408 #endif /* __ASSEMBLY__ */ 409 #endif /* GICV3_H */ 410