1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV2_H__ 8 #define __GICV2_H__ 9 10 /******************************************************************************* 11 * GICv2 miscellaneous definitions 12 ******************************************************************************/ 13 /* Interrupt IDs reported by the HPPIR and IAR registers */ 14 #define PENDING_G1_INTID 1022 15 16 /* GICv2 can only target up to 8 PEs */ 17 #define GICV2_MAX_TARGET_PE 8 18 19 /******************************************************************************* 20 * GICv2 specific Distributor interface register offsets and constants. 21 ******************************************************************************/ 22 #define GICD_ITARGETSR 0x800 23 #define GICD_SGIR 0xF00 24 #define GICD_CPENDSGIR 0xF10 25 #define GICD_SPENDSGIR 0xF20 26 #define GICD_PIDR2_GICV2 0xFE8 27 28 #define ITARGETSR_SHIFT 2 29 #define GIC_TARGET_CPU_MASK 0xff 30 31 #define CPENDSGIR_SHIFT 2 32 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 33 34 /******************************************************************************* 35 * GICv2 specific CPU interface register offsets and constants. 36 ******************************************************************************/ 37 /* Physical CPU Interface registers */ 38 #define GICC_CTLR 0x0 39 #define GICC_PMR 0x4 40 #define GICC_BPR 0x8 41 #define GICC_IAR 0xC 42 #define GICC_EOIR 0x10 43 #define GICC_RPR 0x14 44 #define GICC_HPPIR 0x18 45 #define GICC_AHPPIR 0x28 46 #define GICC_IIDR 0xFC 47 #define GICC_DIR 0x1000 48 #define GICC_PRIODROP GICC_EOIR 49 50 /* GICC_CTLR bit definitions */ 51 #define EOI_MODE_NS (1 << 10) 52 #define EOI_MODE_S (1 << 9) 53 #define IRQ_BYP_DIS_GRP1 (1 << 8) 54 #define FIQ_BYP_DIS_GRP1 (1 << 7) 55 #define IRQ_BYP_DIS_GRP0 (1 << 6) 56 #define FIQ_BYP_DIS_GRP0 (1 << 5) 57 #define CBPR (1 << 4) 58 #define FIQ_EN_SHIFT 3 59 #define FIQ_EN_BIT (1 << FIQ_EN_SHIFT) 60 #define ACK_CTL (1 << 2) 61 62 /* GICC_IIDR bit masks and shifts */ 63 #define GICC_IIDR_PID_SHIFT 20 64 #define GICC_IIDR_ARCH_SHIFT 16 65 #define GICC_IIDR_REV_SHIFT 12 66 #define GICC_IIDR_IMP_SHIFT 0 67 68 #define GICC_IIDR_PID_MASK 0xfff 69 #define GICC_IIDR_ARCH_MASK 0xf 70 #define GICC_IIDR_REV_MASK 0xf 71 #define GICC_IIDR_IMP_MASK 0xfff 72 73 /* HYP view virtual CPU Interface registers */ 74 #define GICH_CTL 0x0 75 #define GICH_VTR 0x4 76 #define GICH_ELRSR0 0x30 77 #define GICH_ELRSR1 0x34 78 #define GICH_APR0 0xF0 79 #define GICH_LR_BASE 0x100 80 81 /* Virtual CPU Interface registers */ 82 #define GICV_CTL 0x0 83 #define GICV_PRIMASK 0x4 84 #define GICV_BP 0x8 85 #define GICV_INTACK 0xC 86 #define GICV_EOI 0x10 87 #define GICV_RUNNINGPRI 0x14 88 #define GICV_HIGHESTPEND 0x18 89 #define GICV_DEACTIVATE 0x1000 90 91 /* GICD_CTLR bit definitions */ 92 #define CTLR_ENABLE_G1_SHIFT 1 93 #define CTLR_ENABLE_G1_MASK 0x1 94 #define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT) 95 96 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 97 #define INT_ID_MASK 0x3ff 98 99 #ifndef __ASSEMBLY__ 100 101 #include <stdint.h> 102 103 /******************************************************************************* 104 * This structure describes some of the implementation defined attributes of 105 * the GICv2 IP. It is used by the platform port to specify these attributes 106 * in order to initialize the GICv2 driver. The attributes are described 107 * below. 108 * 109 * The 'gicd_base' field contains the base address of the Distributor interface 110 * programmer's view. 111 * 112 * The 'gicc_base' field contains the base address of the CPU Interface 113 * programmer's view. 114 * 115 * The 'g0_interrupt_array' field is a pointer to an array in which each 116 * entry corresponds to an ID of a Group 0 interrupt. 117 * 118 * The 'g0_interrupt_num' field contains the number of entries in the 119 * 'g0_interrupt_array'. 120 * 121 * The 'target_masks' is a pointer to an array containing 'target_masks_num' 122 * elements. The GIC driver will populate the array with per-PE target mask to 123 * use to when targeting interrupts. 124 ******************************************************************************/ 125 typedef struct gicv2_driver_data { 126 uintptr_t gicd_base; 127 uintptr_t gicc_base; 128 unsigned int g0_interrupt_num; 129 const unsigned int *g0_interrupt_array; 130 unsigned int *target_masks; 131 unsigned int target_masks_num; 132 } gicv2_driver_data_t; 133 134 /******************************************************************************* 135 * Function prototypes 136 ******************************************************************************/ 137 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); 138 void gicv2_distif_init(void); 139 void gicv2_pcpu_distif_init(void); 140 void gicv2_cpuif_enable(void); 141 void gicv2_cpuif_disable(void); 142 unsigned int gicv2_is_fiq_enabled(void); 143 unsigned int gicv2_get_pending_interrupt_type(void); 144 unsigned int gicv2_get_pending_interrupt_id(void); 145 unsigned int gicv2_acknowledge_interrupt(void); 146 void gicv2_end_of_interrupt(unsigned int id); 147 unsigned int gicv2_get_interrupt_group(unsigned int id); 148 unsigned int gicv2_get_running_priority(void); 149 void gicv2_set_pe_target_mask(unsigned int proc_num); 150 151 #endif /* __ASSEMBLY__ */ 152 #endif /* __GICV2_H__ */ 153