1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV2_H__ 8 #define __GICV2_H__ 9 10 /******************************************************************************* 11 * GICv2 miscellaneous definitions 12 ******************************************************************************/ 13 14 /* Interrupt group definitions */ 15 #define GICV2_INTR_GROUP0 U(0) 16 #define GICV2_INTR_GROUP1 U(1) 17 18 /* Interrupt IDs reported by the HPPIR and IAR registers */ 19 #define PENDING_G1_INTID U(1022) 20 21 /* GICv2 can only target up to 8 PEs */ 22 #define GICV2_MAX_TARGET_PE U(8) 23 24 /******************************************************************************* 25 * GICv2 specific Distributor interface register offsets and constants. 26 ******************************************************************************/ 27 #define GICD_ITARGETSR U(0x800) 28 #define GICD_SGIR U(0xF00) 29 #define GICD_CPENDSGIR U(0xF10) 30 #define GICD_SPENDSGIR U(0xF20) 31 #define GICD_PIDR2_GICV2 U(0xFE8) 32 33 #define ITARGETSR_SHIFT 2 34 #define GIC_TARGET_CPU_MASK U(0xff) 35 36 #define CPENDSGIR_SHIFT 2 37 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 38 39 #define SGIR_TGTLSTFLT_SHIFT 24 40 #define SGIR_TGTLSTFLT_MASK U(0x3) 41 #define SGIR_TGTLST_SHIFT 16 42 #define SGIR_TGTLST_MASK U(0xff) 43 #define SGIR_INTID_MASK ULL(0xf) 44 45 #define SGIR_TGT_SPECIFIC U(0) 46 47 #define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \ 48 ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \ 49 (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \ 50 ((intid) & SGIR_INTID_MASK)) 51 52 /******************************************************************************* 53 * GICv2 specific CPU interface register offsets and constants. 54 ******************************************************************************/ 55 /* Physical CPU Interface registers */ 56 #define GICC_CTLR U(0x0) 57 #define GICC_PMR U(0x4) 58 #define GICC_BPR U(0x8) 59 #define GICC_IAR U(0xC) 60 #define GICC_EOIR U(0x10) 61 #define GICC_RPR U(0x14) 62 #define GICC_HPPIR U(0x18) 63 #define GICC_AHPPIR U(0x28) 64 #define GICC_IIDR U(0xFC) 65 #define GICC_DIR U(0x1000) 66 #define GICC_PRIODROP GICC_EOIR 67 68 /* GICC_CTLR bit definitions */ 69 #define EOI_MODE_NS BIT_32(10) 70 #define EOI_MODE_S BIT_32(9) 71 #define IRQ_BYP_DIS_GRP1 BIT_32(8) 72 #define FIQ_BYP_DIS_GRP1 BIT_32(7) 73 #define IRQ_BYP_DIS_GRP0 BIT_32(6) 74 #define FIQ_BYP_DIS_GRP0 BIT_32(5) 75 #define CBPR BIT_32(4) 76 #define FIQ_EN_SHIFT 3 77 #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT) 78 #define ACK_CTL BIT_32(2) 79 80 /* GICC_IIDR bit masks and shifts */ 81 #define GICC_IIDR_PID_SHIFT 20 82 #define GICC_IIDR_ARCH_SHIFT 16 83 #define GICC_IIDR_REV_SHIFT 12 84 #define GICC_IIDR_IMP_SHIFT 0 85 86 #define GICC_IIDR_PID_MASK U(0xfff) 87 #define GICC_IIDR_ARCH_MASK U(0xf) 88 #define GICC_IIDR_REV_MASK U(0xf) 89 #define GICC_IIDR_IMP_MASK U(0xfff) 90 91 /* HYP view virtual CPU Interface registers */ 92 #define GICH_CTL U(0x0) 93 #define GICH_VTR U(0x4) 94 #define GICH_ELRSR0 U(0x30) 95 #define GICH_ELRSR1 U(0x34) 96 #define GICH_APR0 U(0xF0) 97 #define GICH_LR_BASE U(0x100) 98 99 /* Virtual CPU Interface registers */ 100 #define GICV_CTL U(0x0) 101 #define GICV_PRIMASK U(0x4) 102 #define GICV_BP U(0x8) 103 #define GICV_INTACK U(0xC) 104 #define GICV_EOI U(0x10) 105 #define GICV_RUNNINGPRI U(0x14) 106 #define GICV_HIGHESTPEND U(0x18) 107 #define GICV_DEACTIVATE U(0x1000) 108 109 /* GICD_CTLR bit definitions */ 110 #define CTLR_ENABLE_G1_SHIFT 1 111 #define CTLR_ENABLE_G1_MASK U(0x1) 112 #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT) 113 114 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 115 #define INT_ID_MASK U(0x3ff) 116 117 #ifndef __ASSEMBLY__ 118 119 #include <cdefs.h> 120 #include <interrupt_props.h> 121 #include <stdint.h> 122 123 /******************************************************************************* 124 * This structure describes some of the implementation defined attributes of 125 * the GICv2 IP. It is used by the platform port to specify these attributes 126 * in order to initialize the GICv2 driver. The attributes are described 127 * below. 128 * 129 * The 'gicd_base' field contains the base address of the Distributor interface 130 * programmer's view. 131 * 132 * The 'gicc_base' field contains the base address of the CPU Interface 133 * programmer's view. 134 * 135 * The 'g0_interrupt_array' field is a pointer to an array in which each entry 136 * corresponds to an ID of a Group 0 interrupt. This field is ignored when 137 * 'interrupt_props' field is used. This field is deprecated. 138 * 139 * The 'g0_interrupt_num' field contains the number of entries in the 140 * 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is 141 * used. This field is deprecated. 142 * 143 * The 'target_masks' is a pointer to an array containing 'target_masks_num' 144 * elements. The GIC driver will populate the array with per-PE target mask to 145 * use to when targeting interrupts. 146 * 147 * The 'interrupt_props' field is a pointer to an array that enumerates secure 148 * interrupts and their properties. If this field is not NULL, both 149 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored. 150 * 151 * The 'interrupt_props_num' field contains the number of entries in the 152 * 'interrupt_props' array. If this field is non-zero, 'g0_interrupt_num' is 153 * ignored. 154 ******************************************************************************/ 155 typedef struct gicv2_driver_data { 156 uintptr_t gicd_base; 157 uintptr_t gicc_base; 158 #if !ERROR_DEPRECATED 159 unsigned int g0_interrupt_num __deprecated; 160 const unsigned int *g0_interrupt_array __deprecated; 161 #endif 162 unsigned int *target_masks; 163 unsigned int target_masks_num; 164 const interrupt_prop_t *interrupt_props; 165 unsigned int interrupt_props_num; 166 } gicv2_driver_data_t; 167 168 /******************************************************************************* 169 * Function prototypes 170 ******************************************************************************/ 171 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); 172 void gicv2_distif_init(void); 173 void gicv2_pcpu_distif_init(void); 174 void gicv2_cpuif_enable(void); 175 void gicv2_cpuif_disable(void); 176 unsigned int gicv2_is_fiq_enabled(void); 177 unsigned int gicv2_get_pending_interrupt_type(void); 178 unsigned int gicv2_get_pending_interrupt_id(void); 179 unsigned int gicv2_acknowledge_interrupt(void); 180 void gicv2_end_of_interrupt(unsigned int id); 181 unsigned int gicv2_get_interrupt_group(unsigned int id); 182 unsigned int gicv2_get_running_priority(void); 183 void gicv2_set_pe_target_mask(unsigned int proc_num); 184 unsigned int gicv2_get_interrupt_active(unsigned int id); 185 void gicv2_enable_interrupt(unsigned int id); 186 void gicv2_disable_interrupt(unsigned int id); 187 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); 188 void gicv2_set_interrupt_type(unsigned int id, unsigned int type); 189 void gicv2_raise_sgi(int sgi_num, int proc_num); 190 void gicv2_set_spi_routing(unsigned int id, int proc_num); 191 void gicv2_set_interrupt_pending(unsigned int id); 192 void gicv2_clear_interrupt_pending(unsigned int id); 193 unsigned int gicv2_set_pmr(unsigned int mask); 194 195 #endif /* __ASSEMBLY__ */ 196 #endif /* __GICV2_H__ */ 197