1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __GICV2_H__ 32 #define __GICV2_H__ 33 34 /******************************************************************************* 35 * GICv2 miscellaneous definitions 36 ******************************************************************************/ 37 /* Interrupt IDs reported by the HPPIR and IAR registers */ 38 #define PENDING_G1_INTID 1022 39 40 /******************************************************************************* 41 * GICv2 specific Distributor interface register offsets and constants. 42 ******************************************************************************/ 43 #define GICD_ITARGETSR 0x800 44 #define GICD_SGIR 0xF00 45 #define GICD_CPENDSGIR 0xF10 46 #define GICD_SPENDSGIR 0xF20 47 #define GICD_PIDR2_GICV2 0xFE8 48 49 #define ITARGETSR_SHIFT 2 50 #define GIC_TARGET_CPU_MASK 0xff 51 52 #define CPENDSGIR_SHIFT 2 53 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 54 55 /******************************************************************************* 56 * GICv2 specific CPU interface register offsets and constants. 57 ******************************************************************************/ 58 /* Physical CPU Interface registers */ 59 #define GICC_CTLR 0x0 60 #define GICC_PMR 0x4 61 #define GICC_BPR 0x8 62 #define GICC_IAR 0xC 63 #define GICC_EOIR 0x10 64 #define GICC_RPR 0x14 65 #define GICC_HPPIR 0x18 66 #define GICC_AHPPIR 0x28 67 #define GICC_IIDR 0xFC 68 #define GICC_DIR 0x1000 69 #define GICC_PRIODROP GICC_EOIR 70 71 /* GICC_CTLR bit definitions */ 72 #define EOI_MODE_NS (1 << 10) 73 #define EOI_MODE_S (1 << 9) 74 #define IRQ_BYP_DIS_GRP1 (1 << 8) 75 #define FIQ_BYP_DIS_GRP1 (1 << 7) 76 #define IRQ_BYP_DIS_GRP0 (1 << 6) 77 #define FIQ_BYP_DIS_GRP0 (1 << 5) 78 #define CBPR (1 << 4) 79 #define FIQ_EN_SHIFT 3 80 #define FIQ_EN_BIT (1 << FIQ_EN_SHIFT) 81 #define ACK_CTL (1 << 2) 82 83 /* GICC_IIDR bit masks and shifts */ 84 #define GICC_IIDR_PID_SHIFT 20 85 #define GICC_IIDR_ARCH_SHIFT 16 86 #define GICC_IIDR_REV_SHIFT 12 87 #define GICC_IIDR_IMP_SHIFT 0 88 89 #define GICC_IIDR_PID_MASK 0xfff 90 #define GICC_IIDR_ARCH_MASK 0xf 91 #define GICC_IIDR_REV_MASK 0xf 92 #define GICC_IIDR_IMP_MASK 0xfff 93 94 /* HYP view virtual CPU Interface registers */ 95 #define GICH_CTL 0x0 96 #define GICH_VTR 0x4 97 #define GICH_ELRSR0 0x30 98 #define GICH_ELRSR1 0x34 99 #define GICH_APR0 0xF0 100 #define GICH_LR_BASE 0x100 101 102 /* Virtual CPU Interface registers */ 103 #define GICV_CTL 0x0 104 #define GICV_PRIMASK 0x4 105 #define GICV_BP 0x8 106 #define GICV_INTACK 0xC 107 #define GICV_EOI 0x10 108 #define GICV_RUNNINGPRI 0x14 109 #define GICV_HIGHESTPEND 0x18 110 #define GICV_DEACTIVATE 0x1000 111 112 /* GICD_CTLR bit definitions */ 113 #define CTLR_ENABLE_G1_SHIFT 1 114 #define CTLR_ENABLE_G1_MASK 0x1 115 #define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT) 116 117 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 118 #define INT_ID_MASK 0x3ff 119 120 #ifndef __ASSEMBLY__ 121 122 #include <stdint.h> 123 124 /******************************************************************************* 125 * This structure describes some of the implementation defined attributes of 126 * the GICv2 IP. It is used by the platform port to specify these attributes 127 * in order to initialize the GICv2 driver. The attributes are described 128 * below. 129 * 130 * 1. The 'gicd_base' field contains the base address of the Distributor 131 * interface programmer's view. 132 * 133 * 2. The 'gicc_base' field contains the base address of the CPU Interface 134 * programmer's view. 135 * 136 * 3. The 'g0_interrupt_array' field is a pointer to an array in which each 137 * entry corresponds to an ID of a Group 0 interrupt. 138 * 139 * 4. The 'g0_interrupt_num' field contains the number of entries in the 140 * 'g0_interrupt_array'. 141 ******************************************************************************/ 142 typedef struct gicv2_driver_data { 143 uintptr_t gicd_base; 144 uintptr_t gicc_base; 145 unsigned int g0_interrupt_num; 146 const unsigned int *g0_interrupt_array; 147 } gicv2_driver_data_t; 148 149 /******************************************************************************* 150 * Function prototypes 151 ******************************************************************************/ 152 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); 153 void gicv2_distif_init(void); 154 void gicv2_pcpu_distif_init(void); 155 void gicv2_cpuif_enable(void); 156 void gicv2_cpuif_disable(void); 157 unsigned int gicv2_is_fiq_enabled(void); 158 unsigned int gicv2_get_pending_interrupt_type(void); 159 unsigned int gicv2_get_pending_interrupt_id(void); 160 unsigned int gicv2_acknowledge_interrupt(void); 161 void gicv2_end_of_interrupt(unsigned int id); 162 unsigned int gicv2_get_interrupt_group(unsigned int id); 163 164 #endif /* __ASSEMBLY__ */ 165 #endif /* __GICV2_H__ */ 166