1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GIC_COMMON_H__ 8 #define __GIC_COMMON_H__ 9 10 /******************************************************************************* 11 * GIC Distributor interface general definitions 12 ******************************************************************************/ 13 /* Constants to categorise interrupts */ 14 #define MIN_SGI_ID 0 15 #define MIN_PPI_ID 16 16 #define MIN_SPI_ID 32 17 #define MAX_SPI_ID 1019 18 19 #define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + 1) 20 #define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID) 21 22 /* Mask for the priority field common to all GIC interfaces */ 23 #define GIC_PRI_MASK 0xff 24 25 /* Constant to indicate a spurious interrupt in all GIC versions */ 26 #define GIC_SPURIOUS_INTERRUPT 1023 27 28 /* Constants to categorise priorities */ 29 #define GIC_HIGHEST_SEC_PRIORITY 0 30 #define GIC_LOWEST_SEC_PRIORITY 127 31 #define GIC_HIGHEST_NS_PRIORITY 128 32 #define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ 33 34 /******************************************************************************* 35 * GIC Distributor interface register offsets that are common to GICv3 & GICv2 36 ******************************************************************************/ 37 #define GICD_CTLR 0x0 38 #define GICD_TYPER 0x4 39 #define GICD_IIDR 0x8 40 #define GICD_IGROUPR 0x80 41 #define GICD_ISENABLER 0x100 42 #define GICD_ICENABLER 0x180 43 #define GICD_ISPENDR 0x200 44 #define GICD_ICPENDR 0x280 45 #define GICD_ISACTIVER 0x300 46 #define GICD_ICACTIVER 0x380 47 #define GICD_IPRIORITYR 0x400 48 #define GICD_ICFGR 0xc00 49 #define GICD_NSACR 0xe00 50 51 /* GICD_CTLR bit definitions */ 52 #define CTLR_ENABLE_G0_SHIFT 0 53 #define CTLR_ENABLE_G0_MASK 0x1 54 #define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT) 55 56 57 /******************************************************************************* 58 * GIC Distributor interface register constants that are common to GICv3 & GICv2 59 ******************************************************************************/ 60 #define PIDR2_ARCH_REV_SHIFT 4 61 #define PIDR2_ARCH_REV_MASK 0xf 62 63 /* GICv3 revision as reported by the PIDR2 register */ 64 #define ARCH_REV_GICV3 0x3 65 /* GICv2 revision as reported by the PIDR2 register */ 66 #define ARCH_REV_GICV2 0x2 67 68 #define IGROUPR_SHIFT 5 69 #define ISENABLER_SHIFT 5 70 #define ICENABLER_SHIFT ISENABLER_SHIFT 71 #define ISPENDR_SHIFT 5 72 #define ICPENDR_SHIFT ISPENDR_SHIFT 73 #define ISACTIVER_SHIFT 5 74 #define ICACTIVER_SHIFT ISACTIVER_SHIFT 75 #define IPRIORITYR_SHIFT 2 76 #define ICFGR_SHIFT 4 77 #define NSACR_SHIFT 4 78 79 /* GICD_TYPER shifts and masks */ 80 #define TYPER_IT_LINES_NO_SHIFT 0 81 #define TYPER_IT_LINES_NO_MASK 0x1f 82 83 /* Value used to initialize Normal world interrupt priorities four at a time */ 84 #define GICD_IPRIORITYR_DEF_VAL \ 85 (GIC_HIGHEST_NS_PRIORITY | \ 86 (GIC_HIGHEST_NS_PRIORITY << 8) | \ 87 (GIC_HIGHEST_NS_PRIORITY << 16) | \ 88 (GIC_HIGHEST_NS_PRIORITY << 24)) 89 90 #endif /* __GIC_COMMON_H__ */ 91