1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GIC_COMMON_H__ 8 #define __GIC_COMMON_H__ 9 10 #include <utils_def.h> 11 12 /******************************************************************************* 13 * GIC Distributor interface general definitions 14 ******************************************************************************/ 15 /* Constants to categorise interrupts */ 16 #define MIN_SGI_ID 0 17 #define MIN_SEC_SGI_ID 8 18 #define MIN_PPI_ID 16 19 #define MIN_SPI_ID 32 20 #define MAX_SPI_ID 1019 21 22 #define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + 1) 23 #define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID) 24 25 /* Mask for the priority field common to all GIC interfaces */ 26 #define GIC_PRI_MASK 0xff 27 28 /* Mask for the configuration field common to all GIC interfaces */ 29 #define GIC_CFG_MASK 0x3 30 31 /* Constant to indicate a spurious interrupt in all GIC versions */ 32 #define GIC_SPURIOUS_INTERRUPT 1023 33 34 /* Interrupt configurations: 2-bit fields with LSB reserved */ 35 #define GIC_INTR_CFG_LEVEL (0 << 1) 36 #define GIC_INTR_CFG_EDGE (1 << 1) 37 38 /* Constants to categorise priorities */ 39 #define GIC_HIGHEST_SEC_PRIORITY U(0x00) 40 #define GIC_LOWEST_SEC_PRIORITY U(0x7f) 41 #define GIC_HIGHEST_NS_PRIORITY U(0x80) 42 #define GIC_LOWEST_NS_PRIORITY U(0xfe) /* 0xff would disable all interrupts */ 43 44 /******************************************************************************* 45 * GIC Distributor interface register offsets that are common to GICv3 & GICv2 46 ******************************************************************************/ 47 #define GICD_CTLR 0x0 48 #define GICD_TYPER 0x4 49 #define GICD_IIDR 0x8 50 #define GICD_IGROUPR 0x80 51 #define GICD_ISENABLER 0x100 52 #define GICD_ICENABLER 0x180 53 #define GICD_ISPENDR 0x200 54 #define GICD_ICPENDR 0x280 55 #define GICD_ISACTIVER 0x300 56 #define GICD_ICACTIVER 0x380 57 #define GICD_IPRIORITYR 0x400 58 #define GICD_ICFGR 0xc00 59 #define GICD_NSACR 0xe00 60 61 /* GICD_CTLR bit definitions */ 62 #define CTLR_ENABLE_G0_SHIFT 0 63 #define CTLR_ENABLE_G0_MASK 0x1 64 #define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT) 65 66 67 /******************************************************************************* 68 * GIC Distributor interface register constants that are common to GICv3 & GICv2 69 ******************************************************************************/ 70 #define PIDR2_ARCH_REV_SHIFT 4 71 #define PIDR2_ARCH_REV_MASK 0xf 72 73 /* GICv3 revision as reported by the PIDR2 register */ 74 #define ARCH_REV_GICV3 0x3 75 /* GICv2 revision as reported by the PIDR2 register */ 76 #define ARCH_REV_GICV2 0x2 77 /* GICv1 revision as reported by the PIDR2 register */ 78 #define ARCH_REV_GICV1 0x1 79 80 #define IGROUPR_SHIFT 5 81 #define ISENABLER_SHIFT 5 82 #define ICENABLER_SHIFT ISENABLER_SHIFT 83 #define ISPENDR_SHIFT 5 84 #define ICPENDR_SHIFT ISPENDR_SHIFT 85 #define ISACTIVER_SHIFT 5 86 #define ICACTIVER_SHIFT ISACTIVER_SHIFT 87 #define IPRIORITYR_SHIFT 2 88 #define ITARGETSR_SHIFT 2 89 #define ICFGR_SHIFT 4 90 #define NSACR_SHIFT 4 91 92 /* GICD_TYPER shifts and masks */ 93 #define TYPER_IT_LINES_NO_SHIFT 0 94 #define TYPER_IT_LINES_NO_MASK 0x1f 95 96 /* Value used to initialize Normal world interrupt priorities four at a time */ 97 #define GICD_IPRIORITYR_DEF_VAL \ 98 (GIC_HIGHEST_NS_PRIORITY | \ 99 (GIC_HIGHEST_NS_PRIORITY << 8) | \ 100 (GIC_HIGHEST_NS_PRIORITY << 16) | \ 101 (GIC_HIGHEST_NS_PRIORITY << 24)) 102 103 #endif /* __GIC_COMMON_H__ */ 104