xref: /rk3399_ARM-atf/include/drivers/arm/gic600ae_fmu.h (revision 2c248ade2e958eed33127b4ea767fbb7499f31a7) 
1*2c248adeSVarun Wadekar /*
2*2c248adeSVarun Wadekar  * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
3*2c248adeSVarun Wadekar  *
4*2c248adeSVarun Wadekar  * SPDX-License-Identifier: BSD-3-Clause
5*2c248adeSVarun Wadekar  */
6*2c248adeSVarun Wadekar 
7*2c248adeSVarun Wadekar #ifndef GIC600AE_FMU_H
8*2c248adeSVarun Wadekar #define GIC600AE_FMU_H
9*2c248adeSVarun Wadekar 
10*2c248adeSVarun Wadekar /*******************************************************************************
11*2c248adeSVarun Wadekar  * GIC600-AE FMU register offsets and constants
12*2c248adeSVarun Wadekar  ******************************************************************************/
13*2c248adeSVarun Wadekar #define GICFMU_ERRFR_LO		U(0x000)
14*2c248adeSVarun Wadekar #define GICFMU_ERRFR_HI		U(0x004)
15*2c248adeSVarun Wadekar #define GICFMU_ERRCTLR_LO	U(0x008)
16*2c248adeSVarun Wadekar #define GICFMU_ERRCTLR_HI	U(0x00C)
17*2c248adeSVarun Wadekar #define GICFMU_ERRSTATUS_LO	U(0x010)
18*2c248adeSVarun Wadekar #define GICFMU_ERRSTATUS_HI	U(0x014)
19*2c248adeSVarun Wadekar #define GICFMU_ERRGSR_LO	U(0xE00)
20*2c248adeSVarun Wadekar #define GICFMU_ERRGSR_HI	U(0xE04)
21*2c248adeSVarun Wadekar #define GICFMU_KEY		U(0xEA0)
22*2c248adeSVarun Wadekar #define GICFMU_PINGCTLR		U(0xEA4)
23*2c248adeSVarun Wadekar #define GICFMU_PINGNOW		U(0xEA8)
24*2c248adeSVarun Wadekar #define GICFMU_SMEN		U(0xEB0)
25*2c248adeSVarun Wadekar #define GICFMU_SMINJERR		U(0xEB4)
26*2c248adeSVarun Wadekar #define GICFMU_PINGMASK_LO	U(0xEC0)
27*2c248adeSVarun Wadekar #define GICFMU_PINGMASK_HI	U(0xEC4)
28*2c248adeSVarun Wadekar #define GICFMU_STATUS		U(0xF00)
29*2c248adeSVarun Wadekar #define GICFMU_ERRIDR		U(0xFC8)
30*2c248adeSVarun Wadekar 
31*2c248adeSVarun Wadekar /* ERRCTLR bits */
32*2c248adeSVarun Wadekar #define FMU_ERRCTLR_ED_BIT	BIT(0)
33*2c248adeSVarun Wadekar #define FMU_ERRCTLR_CE_EN_BIT	BIT(1)
34*2c248adeSVarun Wadekar #define FMU_ERRCTLR_UI_BIT	BIT(2)
35*2c248adeSVarun Wadekar #define FMU_ERRCTLR_CI_BIT	BIT(3)
36*2c248adeSVarun Wadekar 
37*2c248adeSVarun Wadekar /* SMEN constants */
38*2c248adeSVarun Wadekar #define FMU_SMEN_BLK_SHIFT	U(8)
39*2c248adeSVarun Wadekar #define FMU_SMEN_SMID_SHIFT	U(24)
40*2c248adeSVarun Wadekar 
41*2c248adeSVarun Wadekar /* Error record IDs */
42*2c248adeSVarun Wadekar #define FMU_BLK_GICD		U(0)
43*2c248adeSVarun Wadekar #define FMU_BLK_SPICOL		U(1)
44*2c248adeSVarun Wadekar #define FMU_BLK_WAKERQ		U(2)
45*2c248adeSVarun Wadekar #define FMU_BLK_ITS0		U(4)
46*2c248adeSVarun Wadekar #define FMU_BLK_ITS1		U(5)
47*2c248adeSVarun Wadekar #define FMU_BLK_ITS2		U(6)
48*2c248adeSVarun Wadekar #define FMU_BLK_ITS3		U(7)
49*2c248adeSVarun Wadekar #define FMU_BLK_ITS4		U(8)
50*2c248adeSVarun Wadekar #define FMU_BLK_ITS5		U(9)
51*2c248adeSVarun Wadekar #define FMU_BLK_ITS6		U(10)
52*2c248adeSVarun Wadekar #define FMU_BLK_ITS7		U(11)
53*2c248adeSVarun Wadekar #define FMU_BLK_PPI0		U(12)
54*2c248adeSVarun Wadekar #define FMU_BLK_PPI1		U(13)
55*2c248adeSVarun Wadekar #define FMU_BLK_PPI2		U(14)
56*2c248adeSVarun Wadekar #define FMU_BLK_PPI3		U(15)
57*2c248adeSVarun Wadekar #define FMU_BLK_PPI4		U(16)
58*2c248adeSVarun Wadekar #define FMU_BLK_PPI5		U(17)
59*2c248adeSVarun Wadekar #define FMU_BLK_PPI6		U(18)
60*2c248adeSVarun Wadekar #define FMU_BLK_PPI7		U(19)
61*2c248adeSVarun Wadekar #define FMU_BLK_PPI8		U(20)
62*2c248adeSVarun Wadekar #define FMU_BLK_PPI9		U(21)
63*2c248adeSVarun Wadekar #define FMU_BLK_PPI10		U(22)
64*2c248adeSVarun Wadekar #define FMU_BLK_PPI11		U(23)
65*2c248adeSVarun Wadekar #define FMU_BLK_PPI12		U(24)
66*2c248adeSVarun Wadekar #define FMU_BLK_PPI13		U(25)
67*2c248adeSVarun Wadekar #define FMU_BLK_PPI14		U(26)
68*2c248adeSVarun Wadekar #define FMU_BLK_PPI15		U(27)
69*2c248adeSVarun Wadekar #define FMU_BLK_PPI16		U(28)
70*2c248adeSVarun Wadekar #define FMU_BLK_PPI17		U(29)
71*2c248adeSVarun Wadekar #define FMU_BLK_PPI18		U(30)
72*2c248adeSVarun Wadekar #define FMU_BLK_PPI19		U(31)
73*2c248adeSVarun Wadekar #define FMU_BLK_PPI20		U(32)
74*2c248adeSVarun Wadekar #define FMU_BLK_PPI21		U(33)
75*2c248adeSVarun Wadekar #define FMU_BLK_PPI22		U(34)
76*2c248adeSVarun Wadekar #define FMU_BLK_PPI23		U(35)
77*2c248adeSVarun Wadekar #define FMU_BLK_PPI24		U(36)
78*2c248adeSVarun Wadekar #define FMU_BLK_PPI25		U(37)
79*2c248adeSVarun Wadekar #define FMU_BLK_PPI26		U(38)
80*2c248adeSVarun Wadekar #define FMU_BLK_PPI27		U(39)
81*2c248adeSVarun Wadekar #define FMU_BLK_PPI28		U(40)
82*2c248adeSVarun Wadekar #define FMU_BLK_PPI29		U(41)
83*2c248adeSVarun Wadekar #define FMU_BLK_PPI30		U(42)
84*2c248adeSVarun Wadekar #define FMU_BLK_PPI31		U(43)
85*2c248adeSVarun Wadekar #define FMU_BLK_PRESENT_MASK	U(0xFFFFFFFFFFF)
86*2c248adeSVarun Wadekar 
87*2c248adeSVarun Wadekar /* Safety Mechamism limit */
88*2c248adeSVarun Wadekar #define FMU_SMID_GICD_MAX	U(33)
89*2c248adeSVarun Wadekar #define FMU_SMID_SPICOL_MAX	U(5)
90*2c248adeSVarun Wadekar #define FMU_SMID_WAKERQ_MAX	U(2)
91*2c248adeSVarun Wadekar #define FMU_SMID_ITS_MAX	U(14)
92*2c248adeSVarun Wadekar #define FMU_SMID_PPI_MAX	U(12)
93*2c248adeSVarun Wadekar 
94*2c248adeSVarun Wadekar /* MBIST Safety Mechanism ID */
95*2c248adeSVarun Wadekar #define GICD_MBIST_REQ_ERROR	U(23)
96*2c248adeSVarun Wadekar #define GICD_FMU_CLKGATE_ERROR	U(33)
97*2c248adeSVarun Wadekar #define PPI_MBIST_REQ_ERROR	U(10)
98*2c248adeSVarun Wadekar #define PPI_FMU_CLKGATE_ERROR	U(12)
99*2c248adeSVarun Wadekar #define ITS_MBIST_REQ_ERROR	U(13)
100*2c248adeSVarun Wadekar #define ITS_FMU_CLKGATE_ERROR	U(14)
101*2c248adeSVarun Wadekar 
102*2c248adeSVarun Wadekar /* ERRSTATUS bits */
103*2c248adeSVarun Wadekar #define FMU_ERRSTATUS_V_BIT	BIT(30)
104*2c248adeSVarun Wadekar #define FMU_ERRSTATUS_UE_BIT	BIT(29)
105*2c248adeSVarun Wadekar #define FMU_ERRSTATUS_OV_BIT	BIT(27)
106*2c248adeSVarun Wadekar #define FMU_ERRSTATUS_CE_BITS	(BIT(25) | BIT(24))
107*2c248adeSVarun Wadekar #define FMU_ERRSTATUS_CLEAR	(FMU_ERRSTATUS_V_BIT | FMU_ERRSTATUS_UE_BIT | \
108*2c248adeSVarun Wadekar 				 FMU_ERRSTATUS_OV_BIT | FMU_ERRSTATUS_CE_BITS)
109*2c248adeSVarun Wadekar 
110*2c248adeSVarun Wadekar /* PINGCTLR constants */
111*2c248adeSVarun Wadekar #define FMU_PINGCTLR_INTDIFF_SHIFT	U(16)
112*2c248adeSVarun Wadekar #define FMU_PINGCTLR_TIMEOUTVAL_SHIFT	U(4)
113*2c248adeSVarun Wadekar #define FMU_PINGCTLR_EN_BIT		BIT(0)
114*2c248adeSVarun Wadekar 
115*2c248adeSVarun Wadekar #ifndef __ASSEMBLER__
116*2c248adeSVarun Wadekar 
117*2c248adeSVarun Wadekar #include <stdint.h>
118*2c248adeSVarun Wadekar 
119*2c248adeSVarun Wadekar #include <arch_helpers.h>
120*2c248adeSVarun Wadekar 
121*2c248adeSVarun Wadekar /*******************************************************************************
122*2c248adeSVarun Wadekar  * GIC600 FMU EL3 driver API
123*2c248adeSVarun Wadekar  ******************************************************************************/
124*2c248adeSVarun Wadekar uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n);
125*2c248adeSVarun Wadekar uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n);
126*2c248adeSVarun Wadekar uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n);
127*2c248adeSVarun Wadekar uint64_t gic_fmu_read_errgsr(uintptr_t base);
128*2c248adeSVarun Wadekar uint32_t gic_fmu_read_pingctlr(uintptr_t base);
129*2c248adeSVarun Wadekar uint32_t gic_fmu_read_pingnow(uintptr_t base);
130*2c248adeSVarun Wadekar uint64_t gic_fmu_read_pingmask(uintptr_t base);
131*2c248adeSVarun Wadekar uint32_t gic_fmu_read_status(uintptr_t base);
132*2c248adeSVarun Wadekar uint32_t gic_fmu_read_erridr(uintptr_t base);
133*2c248adeSVarun Wadekar void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val);
134*2c248adeSVarun Wadekar void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val);
135*2c248adeSVarun Wadekar void gic_fmu_write_pingctlr(uintptr_t base, uint32_t val);
136*2c248adeSVarun Wadekar void gic_fmu_write_pingnow(uintptr_t base, uint32_t val);
137*2c248adeSVarun Wadekar void gic_fmu_write_smen(uintptr_t base, uint32_t val);
138*2c248adeSVarun Wadekar void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val);
139*2c248adeSVarun Wadekar void gic_fmu_write_pingmask(uintptr_t base, uint64_t val);
140*2c248adeSVarun Wadekar 
141*2c248adeSVarun Wadekar void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask, bool errctlr_ce_en, bool errctlr_ue_en);
142*2c248adeSVarun Wadekar void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask,
143*2c248adeSVarun Wadekar 		unsigned int timeout_val, unsigned int interval_diff);
144*2c248adeSVarun Wadekar void gic600_fmu_print_sm_info(uint64_t base, unsigned int blk, unsigned int smid);
145*2c248adeSVarun Wadekar 
146*2c248adeSVarun Wadekar #endif /* __ASSEMBLER__ */
147*2c248adeSVarun Wadekar 
148*2c248adeSVarun Wadekar #endif /* GIC600AE_FMU_H */
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