1*fcc337cfSVijayenthiran Subramaniam /* 2*fcc337cfSVijayenthiran Subramaniam * Copyright (c) 2019, ARM Limited. All rights reserved. 3*fcc337cfSVijayenthiran Subramaniam * 4*fcc337cfSVijayenthiran Subramaniam * SPDX-License-Identifier: BSD-3-Clause 5*fcc337cfSVijayenthiran Subramaniam */ 6*fcc337cfSVijayenthiran Subramaniam 7*fcc337cfSVijayenthiran Subramaniam #ifndef GIC600_MULTICHIP_H 8*fcc337cfSVijayenthiran Subramaniam #define GIC600_MULTICHIP_H 9*fcc337cfSVijayenthiran Subramaniam 10*fcc337cfSVijayenthiran Subramaniam #include <stdint.h> 11*fcc337cfSVijayenthiran Subramaniam 12*fcc337cfSVijayenthiran Subramaniam /* 13*fcc337cfSVijayenthiran Subramaniam * GIC-600 microarchitecture supports coherent multichip environments containing 14*fcc337cfSVijayenthiran Subramaniam * up to 16 chips. 15*fcc337cfSVijayenthiran Subramaniam */ 16*fcc337cfSVijayenthiran Subramaniam #define GIC600_MAX_MULTICHIP 16 17*fcc337cfSVijayenthiran Subramaniam 18*fcc337cfSVijayenthiran Subramaniam /* SPI IDs array consist of min and max ids */ 19*fcc337cfSVijayenthiran Subramaniam #define GIC600_SPI_IDS_SIZE 2 20*fcc337cfSVijayenthiran Subramaniam 21*fcc337cfSVijayenthiran Subramaniam /******************************************************************************* 22*fcc337cfSVijayenthiran Subramaniam * GIC-600 multichip data structure describes platform specific attributes 23*fcc337cfSVijayenthiran Subramaniam * related to GIC-600 multichip. Platform port is expected to define these 24*fcc337cfSVijayenthiran Subramaniam * attributes to initialize the multichip related registers and create 25*fcc337cfSVijayenthiran Subramaniam * successful connections between the GIC-600s in a multichip system. 26*fcc337cfSVijayenthiran Subramaniam * 27*fcc337cfSVijayenthiran Subramaniam * The 'rt_owner_base' field contains the base address of the GIC Distributor 28*fcc337cfSVijayenthiran Subramaniam * which owns the routing table. 29*fcc337cfSVijayenthiran Subramaniam * 30*fcc337cfSVijayenthiran Subramaniam * The 'rt_owner' field contains the chip number which owns the routing table. 31*fcc337cfSVijayenthiran Subramaniam * Chip number or chip_id starts from 0. 32*fcc337cfSVijayenthiran Subramaniam * 33*fcc337cfSVijayenthiran Subramaniam * The 'chip_count' field contains the total number of chips in a multichip 34*fcc337cfSVijayenthiran Subramaniam * system. This should match the number of entries in 'chip_addrs' and 'spi_ids' 35*fcc337cfSVijayenthiran Subramaniam * fields. 36*fcc337cfSVijayenthiran Subramaniam * 37*fcc337cfSVijayenthiran Subramaniam * The 'chip_addrs' field contains array of chip addresses. These addresses are 38*fcc337cfSVijayenthiran Subramaniam * implementation specific values. 39*fcc337cfSVijayenthiran Subramaniam * 40*fcc337cfSVijayenthiran Subramaniam * The 'spi_ids' field contains array of minimum and maximum SPI interrupt ids 41*fcc337cfSVijayenthiran Subramaniam * that each chip owns. Note that SPI interrupt ids can range from 32 to 960 and 42*fcc337cfSVijayenthiran Subramaniam * it should be group of 32 (i.e., SPI minimum and (SPI maximum + 1) should be 43*fcc337cfSVijayenthiran Subramaniam * a multiple of 32). If a chip doesn't own any SPI interrupts a value of {0, 0} 44*fcc337cfSVijayenthiran Subramaniam * should be passed. 45*fcc337cfSVijayenthiran Subramaniam ******************************************************************************/ 46*fcc337cfSVijayenthiran Subramaniam struct gic600_multichip_data { 47*fcc337cfSVijayenthiran Subramaniam uintptr_t rt_owner_base; 48*fcc337cfSVijayenthiran Subramaniam unsigned int rt_owner; 49*fcc337cfSVijayenthiran Subramaniam unsigned int chip_count; 50*fcc337cfSVijayenthiran Subramaniam uint64_t chip_addrs[GIC600_MAX_MULTICHIP]; 51*fcc337cfSVijayenthiran Subramaniam unsigned int spi_ids[GIC600_MAX_MULTICHIP][GIC600_SPI_IDS_SIZE]; 52*fcc337cfSVijayenthiran Subramaniam }; 53*fcc337cfSVijayenthiran Subramaniam 54*fcc337cfSVijayenthiran Subramaniam void gic600_multichip_init(struct gic600_multichip_data *multichip_data); 55*fcc337cfSVijayenthiran Subramaniam #endif /* GIC600_MULTICHIP_H */ 56