1fcc337cfSVijayenthiran Subramaniam /* 2fcc337cfSVijayenthiran Subramaniam * Copyright (c) 2019, ARM Limited. All rights reserved. 3*a02a45dfSVarun Wadekar * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4fcc337cfSVijayenthiran Subramaniam * 5fcc337cfSVijayenthiran Subramaniam * SPDX-License-Identifier: BSD-3-Clause 6fcc337cfSVijayenthiran Subramaniam */ 7fcc337cfSVijayenthiran Subramaniam 8fcc337cfSVijayenthiran Subramaniam #ifndef GIC600_MULTICHIP_H 9fcc337cfSVijayenthiran Subramaniam #define GIC600_MULTICHIP_H 10fcc337cfSVijayenthiran Subramaniam 11fcc337cfSVijayenthiran Subramaniam #include <stdint.h> 12fcc337cfSVijayenthiran Subramaniam 13fcc337cfSVijayenthiran Subramaniam /* 14fcc337cfSVijayenthiran Subramaniam * GIC-600 microarchitecture supports coherent multichip environments containing 15fcc337cfSVijayenthiran Subramaniam * up to 16 chips. 16fcc337cfSVijayenthiran Subramaniam */ 17fcc337cfSVijayenthiran Subramaniam #define GIC600_MAX_MULTICHIP 16 18fcc337cfSVijayenthiran Subramaniam 19*a02a45dfSVarun Wadekar typedef struct multichip_spi_ids_desc { 20*a02a45dfSVarun Wadekar uintptr_t gicd_base; 21*a02a45dfSVarun Wadekar uint32_t spi_id_min; 22*a02a45dfSVarun Wadekar uint32_t spi_id_max; 23*a02a45dfSVarun Wadekar } multichip_spi_ids_desc_t; 24fcc337cfSVijayenthiran Subramaniam 25fcc337cfSVijayenthiran Subramaniam /******************************************************************************* 26fcc337cfSVijayenthiran Subramaniam * GIC-600 multichip data structure describes platform specific attributes 27fcc337cfSVijayenthiran Subramaniam * related to GIC-600 multichip. Platform port is expected to define these 28fcc337cfSVijayenthiran Subramaniam * attributes to initialize the multichip related registers and create 29fcc337cfSVijayenthiran Subramaniam * successful connections between the GIC-600s in a multichip system. 30fcc337cfSVijayenthiran Subramaniam * 31fcc337cfSVijayenthiran Subramaniam * The 'rt_owner_base' field contains the base address of the GIC Distributor 32fcc337cfSVijayenthiran Subramaniam * which owns the routing table. 33fcc337cfSVijayenthiran Subramaniam * 34fcc337cfSVijayenthiran Subramaniam * The 'rt_owner' field contains the chip number which owns the routing table. 35fcc337cfSVijayenthiran Subramaniam * Chip number or chip_id starts from 0. 36fcc337cfSVijayenthiran Subramaniam * 37fcc337cfSVijayenthiran Subramaniam * The 'chip_count' field contains the total number of chips in a multichip 38fcc337cfSVijayenthiran Subramaniam * system. This should match the number of entries in 'chip_addrs' and 'spi_ids' 39fcc337cfSVijayenthiran Subramaniam * fields. 40fcc337cfSVijayenthiran Subramaniam * 41fcc337cfSVijayenthiran Subramaniam * The 'chip_addrs' field contains array of chip addresses. These addresses are 42fcc337cfSVijayenthiran Subramaniam * implementation specific values. 43fcc337cfSVijayenthiran Subramaniam * 44*a02a45dfSVarun Wadekar * The 'multichip_spi_ids_desc_t' field contains array of descriptors used to 45*a02a45dfSVarun Wadekar * provide minimum and maximum SPI interrupt ids that each chip owns and the 46*a02a45dfSVarun Wadekar * corresponding chip base address. Note that SPI interrupt ids can range from 47*a02a45dfSVarun Wadekar * 32 to 960 and it should be group of 32 (i.e., SPI minimum and (SPI maximum + 48*a02a45dfSVarun Wadekar * 1) should be a multiple of 32). If a chip doesn't own any SPI interrupts a 49*a02a45dfSVarun Wadekar * value of {0, 0, 0} should be passed. 50fcc337cfSVijayenthiran Subramaniam ******************************************************************************/ 51fcc337cfSVijayenthiran Subramaniam struct gic600_multichip_data { 52fcc337cfSVijayenthiran Subramaniam uintptr_t rt_owner_base; 53fcc337cfSVijayenthiran Subramaniam unsigned int rt_owner; 54fcc337cfSVijayenthiran Subramaniam unsigned int chip_count; 55fcc337cfSVijayenthiran Subramaniam uint64_t chip_addrs[GIC600_MAX_MULTICHIP]; 56*a02a45dfSVarun Wadekar multichip_spi_ids_desc_t spi_ids[GIC600_MAX_MULTICHIP]; 57fcc337cfSVijayenthiran Subramaniam }; 58fcc337cfSVijayenthiran Subramaniam 59*a02a45dfSVarun Wadekar uintptr_t gic600_multichip_gicd_base_for_spi(uint32_t spi_id); 60fcc337cfSVijayenthiran Subramaniam void gic600_multichip_init(struct gic600_multichip_data *multichip_data); 61*a02a45dfSVarun Wadekar bool gic600_multichip_is_initialized(void); 62*a02a45dfSVarun Wadekar 63fcc337cfSVijayenthiran Subramaniam #endif /* GIC600_MULTICHIP_H */ 64