1*d38c64d2SGovindraj Raja /* 2*d38c64d2SGovindraj Raja * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved. 3*d38c64d2SGovindraj Raja * 4*d38c64d2SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5*d38c64d2SGovindraj Raja */ 6*d38c64d2SGovindraj Raja 7*d38c64d2SGovindraj Raja #ifndef FVP_CPU_PWR_H 8*d38c64d2SGovindraj Raja #define FVP_CPU_PWR_H 9*d38c64d2SGovindraj Raja 10*d38c64d2SGovindraj Raja #ifndef __ASSEMBLER__ 11*d38c64d2SGovindraj Raja #include <stdbool.h> 12*d38c64d2SGovindraj Raja #include <stdint.h> 13*d38c64d2SGovindraj Raja 14*d38c64d2SGovindraj Raja #if __aarch64__ 15*d38c64d2SGovindraj Raja bool check_cpupwrctrl_el1_is_available(void); 16*d38c64d2SGovindraj Raja #endif /* __aarch64__ */ 17*d38c64d2SGovindraj Raja #endif /* __ASSEMBLER__ */ 18*d38c64d2SGovindraj Raja 19*d38c64d2SGovindraj Raja /******************************************************************************* 20*d38c64d2SGovindraj Raja * CPU Power Control register specific definitions 21*d38c64d2SGovindraj Raja ******************************************************************************/ 22*d38c64d2SGovindraj Raja #define CPUPWRCTLR_EL1 S3_0_C15_C2_7 23*d38c64d2SGovindraj Raja #define CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 24*d38c64d2SGovindraj Raja 25*d38c64d2SGovindraj Raja #endif /* FVP_CPU_PWR_H */ 26