1 /* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ETHOSN_H 8 #define ETHOSN_H 9 10 #include <lib/smccc.h> 11 12 /* Function numbers */ 13 #define ETHOSN_FNUM_VERSION U(0x50) 14 #define ETHOSN_FNUM_IS_SEC U(0x51) 15 #define ETHOSN_FNUM_HARD_RESET U(0x52) 16 #define ETHOSN_FNUM_SOFT_RESET U(0x53) 17 #define ETHOSN_FNUM_IS_SLEEPING U(0x54) 18 #define ETHOSN_FNUM_GET_FW_PROP U(0x55) 19 /* 0x56-0x5F reserved for future use */ 20 21 /* Properties for ETHOSN_FNUM_TZMP_GET_FW_PROP */ 22 #define ETHOSN_FW_PROP_VERSION U(0xF00) 23 #define ETHOSN_FW_PROP_MEM_INFO U(0xF01) 24 #define ETHOSN_FW_PROP_OFFSETS U(0xF02) 25 #define ETHOSN_FW_PROP_VA_MAP U(0xF03) 26 27 /* SMC64 function IDs */ 28 #define ETHOSN_FID_64(func_num) U(0xC2000000 | func_num) 29 #define ETHOSN_FID_VERSION_64 ETHOSN_FID_64(ETHOSN_FNUM_VERSION) 30 #define ETHOSN_FID_IS_SEC_64 ETHOSN_FID_64(ETHOSN_FNUM_IS_SEC) 31 #define ETHOSN_FID_HARD_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_HARD_RESET) 32 #define ETHOSN_FID_SOFT_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_SOFT_RESET) 33 34 /* SMC32 function IDs */ 35 #define ETHOSN_FID_32(func_num) U(0x82000000 | func_num) 36 #define ETHOSN_FID_VERSION_32 ETHOSN_FID_32(ETHOSN_FNUM_VERSION) 37 #define ETHOSN_FID_IS_SEC_32 ETHOSN_FID_32(ETHOSN_FNUM_IS_SEC) 38 #define ETHOSN_FID_HARD_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_HARD_RESET) 39 #define ETHOSN_FID_SOFT_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_SOFT_RESET) 40 41 #define ETHOSN_NUM_SMC_CALLS 8 42 43 /* Macro to identify function calls */ 44 #define ETHOSN_FID_MASK U(0xFFF0) 45 #define ETHOSN_FID_VALUE U(0x50) 46 #define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE) 47 48 /* Service version */ 49 #define ETHOSN_VERSION_MAJOR U(2) 50 #define ETHOSN_VERSION_MINOR U(6) 51 52 /* Return codes for function calls */ 53 #define ETHOSN_SUCCESS 0 54 #define ETHOSN_NOT_SUPPORTED -1 55 /* -2 Reserved for NOT_REQUIRED */ 56 #define ETHOSN_INVALID_PARAMETER -3 57 #define ETHOSN_FAILURE -4 58 #define ETHOSN_UNKNOWN_CORE_ADDRESS -5 59 #define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6 60 #define ETHOSN_INVALID_CONFIGURATION -7 61 62 /* 63 * Argument types for soft and hard resets to indicate whether to reset 64 * and reconfigure the NPU or only halt it 65 */ 66 #define ETHOSN_RESET_TYPE_FULL U(0) 67 #define ETHOSN_RESET_TYPE_HALT U(1) 68 69 int ethosn_smc_setup(void); 70 71 uintptr_t ethosn_smc_handler(uint32_t smc_fid, 72 u_register_t core_addr, 73 u_register_t asset_alloc_idx, 74 u_register_t reset_type, 75 u_register_t x4, 76 void *cookie, 77 void *handle, 78 u_register_t flags); 79 80 #endif /* ETHOSN_H */ 81