1 /* 2 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DSU_H 8 #define DSU_H 9 10 #if defined(__aarch64__) 11 #include <dsu_def.h> 12 13 /* 14 * Power Control Registers enable bit of Auxilary Control register. 15 * ACTLR_EL3_PWREN_BIT definition is same among cores like Cortex-X925, 16 * Cortex-X4, Cortex-A520, Cortex-A725 that are used in a cluster 17 * with DSU. 18 */ 19 #define ACTLR_EL3_PWREN_BIT BIT(7) 20 21 #define PMCR_N_MAX 0x1f 22 23 #define save_pmu_reg(state, reg) state->reg = read_##reg() 24 25 #define restore_pmu_reg(context, reg) write_##reg(context->reg) 26 27 typedef struct cluster_pmu_state { 28 uint64_t clusterpmcr; 29 uint64_t clusterpmcntenset; 30 uint64_t clusterpmccntr; 31 uint64_t clusterpmovsset; 32 uint64_t clusterpmselr; 33 uint64_t clusterpmsevtyper; 34 uint64_t counter_val[PMCR_N_MAX]; 35 uint64_t counter_type[PMCR_N_MAX]; 36 } cluster_pmu_state_t; 37 38 typedef struct dsu_driver_data { 39 uint8_t clusterpwrdwn_pwrdn; 40 uint8_t clusterpwrdwn_memret; 41 uint8_t clusterpwrctlr_cachepwr; 42 uint8_t clusterpwrctlr_funcret; 43 } dsu_driver_data_t; 44 45 extern const dsu_driver_data_t plat_dsu_data; 46 47 static inline unsigned int read_cluster_eventctr_num(void) 48 { 49 return ((read_clusterpmcr() >> CLUSTERPMCR_N_SHIFT) & 50 CLUSTERPMCR_N_MASK); 51 } 52 53 void save_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context); 54 55 void restore_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context); 56 57 void cluster_on_dsu_pmu_context_restore(void); 58 59 void cluster_off_dsu_pmu_context_save(void); 60 61 void dsu_driver_init(const dsu_driver_data_t *data); 62 #endif 63 #endif /* DSU_H */ 64