1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CCI_H__ 32 #define __CCI_H__ 33 34 /* Slave interface offsets from PERIPHBASE */ 35 #define SLAVE_IFACE6_OFFSET 0x7000 36 #define SLAVE_IFACE5_OFFSET 0x6000 37 #define SLAVE_IFACE4_OFFSET 0x5000 38 #define SLAVE_IFACE3_OFFSET 0x4000 39 #define SLAVE_IFACE2_OFFSET 0x3000 40 #define SLAVE_IFACE1_OFFSET 0x2000 41 #define SLAVE_IFACE0_OFFSET 0x1000 42 #define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \ 43 (0x1000 * (index))) 44 45 /* Slave interface event and count register offsets from PERIPHBASE */ 46 #define EVENT_SELECT7_OFFSET 0x80000 47 #define EVENT_SELECT6_OFFSET 0x70000 48 #define EVENT_SELECT5_OFFSET 0x60000 49 #define EVENT_SELECT4_OFFSET 0x50000 50 #define EVENT_SELECT3_OFFSET 0x40000 51 #define EVENT_SELECT2_OFFSET 0x30000 52 #define EVENT_SELECT1_OFFSET 0x20000 53 #define EVENT_SELECT0_OFFSET 0x10000 54 #define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \ 55 (0x10000 * (index))) 56 57 /* Control and ID register offsets */ 58 #define CTRL_OVERRIDE_REG 0x0 59 #define SECURE_ACCESS_REG 0x8 60 #define STATUS_REG 0xc 61 #define IMPRECISE_ERR_REG 0x10 62 #define PERFMON_CTRL_REG 0x100 63 #define IFACE_MON_CTRL_REG 0x104 64 65 /* Component and peripheral ID registers */ 66 #define PERIPHERAL_ID0 0xFE0 67 #define PERIPHERAL_ID1 0xFE4 68 #define PERIPHERAL_ID2 0xFE8 69 #define PERIPHERAL_ID3 0xFEC 70 #define PERIPHERAL_ID4 0xFD0 71 #define PERIPHERAL_ID5 0xFD4 72 #define PERIPHERAL_ID6 0xFD8 73 #define PERIPHERAL_ID7 0xFDC 74 75 #define COMPONENT_ID0 0xFF0 76 #define COMPONENT_ID1 0xFF4 77 #define COMPONENT_ID2 0xFF8 78 #define COMPONENT_ID3 0xFFC 79 #define COMPONENT_ID4 0x1000 80 #define COMPONENT_ID5 0x1004 81 #define COMPONENT_ID6 0x1008 82 #define COMPONENT_ID7 0x100C 83 84 /* Slave interface register offsets */ 85 #define SNOOP_CTRL_REG 0x0 86 #define SH_OVERRIDE_REG 0x4 87 #define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 88 #define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 89 #define MAX_OT_REG 0x110 90 91 /* Snoop Control register bit definitions */ 92 #define DVM_EN_BIT (1 << 1) 93 #define SNOOP_EN_BIT (1 << 0) 94 #define SUPPORT_SNOOPS (1 << 30) 95 #define SUPPORT_DVM (1 << 31) 96 97 /* Status register bit definitions */ 98 #define CHANGE_PENDING_BIT (1 << 0) 99 100 /* Event and count register offsets */ 101 #define EVENT_SELECT_REG 0x0 102 #define EVENT_COUNT_REG 0x4 103 #define COUNT_CNTRL_REG 0x8 104 #define COUNT_OVERFLOW_REG 0xC 105 106 /* Slave interface monitor registers */ 107 #define INT_MON_REG_SI0 0x90000 108 #define INT_MON_REG_SI1 0x90004 109 #define INT_MON_REG_SI2 0x90008 110 #define INT_MON_REG_SI3 0x9000C 111 #define INT_MON_REG_SI4 0x90010 112 #define INT_MON_REG_SI5 0x90014 113 #define INT_MON_REG_SI6 0x90018 114 115 /* Master interface monitor registers */ 116 #define INT_MON_REG_MI0 0x90100 117 #define INT_MON_REG_MI1 0x90104 118 #define INT_MON_REG_MI2 0x90108 119 #define INT_MON_REG_MI3 0x9010c 120 #define INT_MON_REG_MI4 0x90110 121 #define INT_MON_REG_MI5 0x90114 122 123 #define SLAVE_IF_UNUSED -1 124 125 #if ARM_CCI_PRODUCT_ID == 400 126 #define CCI_SLAVE_INTERFACE_COUNT 5 127 #elif ARM_CCI_PRODUCT_ID == 500 128 #define CCI_SLAVE_INTERFACE_COUNT 7 129 #else 130 #error "Invalid CCI product or CCI not supported" 131 #endif 132 133 #ifndef __ASSEMBLY__ 134 135 #include <stdint.h> 136 137 /* Function declarations */ 138 139 /* 140 * The ARM CCI driver needs the following: 141 * 1. Base address of the CCI-500/CCI-400 142 * 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave 143 * interfaces. 144 * 3. Size of the array. 145 * 146 * SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists 147 * for that interface. 148 */ 149 void cci_init(uintptr_t cci_base, 150 const int *map, 151 unsigned int num_cci_masters); 152 153 void cci_enable_snoop_dvm_reqs(unsigned int master_id); 154 void cci_disable_snoop_dvm_reqs(unsigned int master_id); 155 156 #endif /* __ASSEMBLY__ */ 157 #endif /* __CCI_H__ */ 158