1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __EP_INFO_H__ 8 #define __EP_INFO_H__ 9 10 #include <param_header.h> 11 #include <utils_def.h> 12 13 #define SECURE U(0x0) 14 #define NON_SECURE U(0x1) 15 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE)) 16 17 /******************************************************************************* 18 * Constants that allow assembler code to access members of and the 19 * 'entry_point_info' structure at their correct offsets. 20 ******************************************************************************/ 21 #define ENTRY_POINT_INFO_PC_OFFSET U(0x08) 22 #ifdef AARCH32 23 #define ENTRY_POINT_INFO_ARGS_OFFSET U(0x10) 24 #else 25 #define ENTRY_POINT_INFO_ARGS_OFFSET U(0x18) 26 #endif 27 28 /* The following are used to set/get image attributes. */ 29 #define PARAM_EP_SECURITY_MASK U(0x1) 30 31 #define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) 32 #define SET_SECURITY_STATE(x, security) \ 33 ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) 34 35 #define EP_EE_MASK U(0x2) 36 #define EP_EE_LITTLE U(0x0) 37 #define EP_EE_BIG U(0x2) 38 #define EP_GET_EE(x) (x & EP_EE_MASK) 39 #define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) 40 41 #define EP_ST_MASK U(0x4) 42 #define EP_ST_DISABLE U(0x0) 43 #define EP_ST_ENABLE U(0x4) 44 #define EP_GET_ST(x) (x & EP_ST_MASK) 45 #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) 46 47 #define EP_EXE_MASK U(0x8) 48 #define NON_EXECUTABLE U(0x0) 49 #define EXECUTABLE U(0x8) 50 #define EP_GET_EXE(x) (x & EP_EXE_MASK) 51 #define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) 52 53 #define EP_FIRST_EXE_MASK U(0x10) 54 #define EP_FIRST_EXE U(0x10) 55 #define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) 56 #define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) 57 58 #ifndef __ASSEMBLY__ 59 60 #include <cassert.h> 61 #include <types.h> 62 63 typedef struct aapcs64_params { 64 u_register_t arg0; 65 u_register_t arg1; 66 u_register_t arg2; 67 u_register_t arg3; 68 u_register_t arg4; 69 u_register_t arg5; 70 u_register_t arg6; 71 u_register_t arg7; 72 } aapcs64_params_t; 73 74 typedef struct aapcs32_params { 75 u_register_t arg0; 76 u_register_t arg1; 77 u_register_t arg2; 78 u_register_t arg3; 79 } aapcs32_params_t; 80 81 /***************************************************************************** 82 * This structure represents the superset of information needed while 83 * switching exception levels. The only two mechanisms to do so are 84 * ERET & SMC. Security state is indicated using bit zero of header 85 * attribute 86 * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start 87 * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while 88 * processing SMC to jump to BL31. 89 *****************************************************************************/ 90 typedef struct entry_point_info { 91 param_header_t h; 92 uintptr_t pc; 93 uint32_t spsr; 94 #ifdef AARCH32 95 aapcs32_params_t args; 96 #else 97 aapcs64_params_t args; 98 #endif 99 } entry_point_info_t; 100 101 /* 102 * Compile time assertions related to the 'entry_point_info' structure to 103 * ensure that the assembler and the compiler view of the offsets of 104 * the structure members is the same. 105 */ 106 CASSERT(ENTRY_POINT_INFO_PC_OFFSET == 107 __builtin_offsetof(entry_point_info_t, pc), \ 108 assert_BL31_pc_offset_mismatch); 109 110 CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \ 111 __builtin_offsetof(entry_point_info_t, args), \ 112 assert_BL31_args_offset_mismatch); 113 114 CASSERT(sizeof(uintptr_t) == 115 __builtin_offsetof(entry_point_info_t, spsr) - \ 116 __builtin_offsetof(entry_point_info_t, pc), \ 117 assert_entrypoint_and_spsr_should_be_adjacent); 118 119 #endif /*__ASSEMBLY__*/ 120 121 #endif /* __EP_INFO_H__ */ 122 123