xref: /rk3399_ARM-atf/include/common/bl_common.ld.h (revision a7739bc7b16bf3e43f370864f8a800cf8943b391)
1665e71b8SMasahiro Yamada /*
2665e71b8SMasahiro Yamada  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3665e71b8SMasahiro Yamada  *
4665e71b8SMasahiro Yamada  * SPDX-License-Identifier: BSD-3-Clause
5665e71b8SMasahiro Yamada  */
6665e71b8SMasahiro Yamada 
7665e71b8SMasahiro Yamada #ifndef BL_COMMON_LD_H
8665e71b8SMasahiro Yamada #define BL_COMMON_LD_H
9665e71b8SMasahiro Yamada 
109fb288a0SMasahiro Yamada #include <platform_def.h>
119fb288a0SMasahiro Yamada 
129fb288a0SMasahiro Yamada #ifdef __aarch64__
139fb288a0SMasahiro Yamada #define STRUCT_ALIGN	8
14*a7739bc7SMasahiro Yamada #define BSS_ALIGN	16
159fb288a0SMasahiro Yamada #else
169fb288a0SMasahiro Yamada #define STRUCT_ALIGN	4
17*a7739bc7SMasahiro Yamada #define BSS_ALIGN	8
189fb288a0SMasahiro Yamada #endif
199fb288a0SMasahiro Yamada 
209fb288a0SMasahiro Yamada #define CPU_OPS						\
219fb288a0SMasahiro Yamada 	. = ALIGN(STRUCT_ALIGN);			\
229fb288a0SMasahiro Yamada 	__CPU_OPS_START__ = .;				\
239fb288a0SMasahiro Yamada 	KEEP(*(cpu_ops))				\
249fb288a0SMasahiro Yamada 	__CPU_OPS_END__ = .;
259fb288a0SMasahiro Yamada 
269fb288a0SMasahiro Yamada #define PARSER_LIB_DESCS				\
279fb288a0SMasahiro Yamada 	. = ALIGN(STRUCT_ALIGN);			\
289fb288a0SMasahiro Yamada 	__PARSER_LIB_DESCS_START__ = .;			\
299fb288a0SMasahiro Yamada 	KEEP(*(.img_parser_lib_descs))			\
309fb288a0SMasahiro Yamada 	__PARSER_LIB_DESCS_END__ = .;
319fb288a0SMasahiro Yamada 
329fb288a0SMasahiro Yamada #define RT_SVC_DESCS					\
339fb288a0SMasahiro Yamada 	. = ALIGN(STRUCT_ALIGN);			\
349fb288a0SMasahiro Yamada 	__RT_SVC_DESCS_START__ = .;			\
359fb288a0SMasahiro Yamada 	KEEP(*(rt_svc_descs))				\
369fb288a0SMasahiro Yamada 	__RT_SVC_DESCS_END__ = .;
379fb288a0SMasahiro Yamada 
389fb288a0SMasahiro Yamada #define PMF_SVC_DESCS					\
399fb288a0SMasahiro Yamada 	. = ALIGN(STRUCT_ALIGN);			\
409fb288a0SMasahiro Yamada 	__PMF_SVC_DESCS_START__ = .;			\
419fb288a0SMasahiro Yamada 	KEEP(*(pmf_svc_descs))				\
429fb288a0SMasahiro Yamada 	__PMF_SVC_DESCS_END__ = .;
439fb288a0SMasahiro Yamada 
449fb288a0SMasahiro Yamada #define FCONF_POPULATOR					\
459fb288a0SMasahiro Yamada 	. = ALIGN(STRUCT_ALIGN);			\
469fb288a0SMasahiro Yamada 	__FCONF_POPULATOR_START__ = .;			\
479fb288a0SMasahiro Yamada 	KEEP(*(.fconf_populator))			\
489fb288a0SMasahiro Yamada 	__FCONF_POPULATOR_END__ = .;
499fb288a0SMasahiro Yamada 
509fb288a0SMasahiro Yamada /*
519fb288a0SMasahiro Yamada  * Keep the .got section in the RO section as it is patched prior to enabling
529fb288a0SMasahiro Yamada  * the MMU and having the .got in RO is better for security. GOT is a table of
539fb288a0SMasahiro Yamada  * addresses so ensure pointer size alignment.
549fb288a0SMasahiro Yamada  */
559fb288a0SMasahiro Yamada #define GOT						\
569fb288a0SMasahiro Yamada 	. = ALIGN(STRUCT_ALIGN);			\
579fb288a0SMasahiro Yamada 	__GOT_START__ = .;				\
589fb288a0SMasahiro Yamada 	*(.got)						\
599fb288a0SMasahiro Yamada 	__GOT_END__ = .;
609fb288a0SMasahiro Yamada 
610a0a7a9aSMasahiro Yamada #define RODATA_COMMON					\
620a0a7a9aSMasahiro Yamada 	RT_SVC_DESCS					\
630a0a7a9aSMasahiro Yamada 	FCONF_POPULATOR					\
640a0a7a9aSMasahiro Yamada 	PMF_SVC_DESCS					\
650a0a7a9aSMasahiro Yamada 	PARSER_LIB_DESCS				\
660a0a7a9aSMasahiro Yamada 	CPU_OPS						\
670a0a7a9aSMasahiro Yamada 	GOT
680a0a7a9aSMasahiro Yamada 
699fb288a0SMasahiro Yamada #define STACK_SECTION					\
709fb288a0SMasahiro Yamada 	stacks (NOLOAD) : {				\
719fb288a0SMasahiro Yamada 		__STACKS_START__ = .;			\
729fb288a0SMasahiro Yamada 		*(tzfw_normal_stacks)			\
739fb288a0SMasahiro Yamada 		__STACKS_END__ = .;			\
749fb288a0SMasahiro Yamada 	}
759fb288a0SMasahiro Yamada 
769fb288a0SMasahiro Yamada /*
779fb288a0SMasahiro Yamada  * If BL doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__
789fb288a0SMasahiro Yamada  * will be zero. For this reason, the only two valid values for
799fb288a0SMasahiro Yamada  * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value
809fb288a0SMasahiro Yamada  * PLAT_PERCPU_BAKERY_LOCK_SIZE.
819fb288a0SMasahiro Yamada  */
829fb288a0SMasahiro Yamada #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
839fb288a0SMasahiro Yamada #define BAKERY_LOCK_SIZE_CHECK				\
849fb288a0SMasahiro Yamada 	ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) ||	\
859fb288a0SMasahiro Yamada 	       (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE), \
869fb288a0SMasahiro Yamada 	       "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
879fb288a0SMasahiro Yamada #else
889fb288a0SMasahiro Yamada #define BAKERY_LOCK_SIZE_CHECK
899fb288a0SMasahiro Yamada #endif
909fb288a0SMasahiro Yamada 
919fb288a0SMasahiro Yamada /*
929fb288a0SMasahiro Yamada  * Bakery locks are stored in normal .bss memory
939fb288a0SMasahiro Yamada  *
949fb288a0SMasahiro Yamada  * Each lock's data is spread across multiple cache lines, one per CPU,
959fb288a0SMasahiro Yamada  * but multiple locks can share the same cache line.
969fb288a0SMasahiro Yamada  * The compiler will allocate enough memory for one CPU's bakery locks,
979fb288a0SMasahiro Yamada  * the remaining cache lines are allocated by the linker script
989fb288a0SMasahiro Yamada  */
999fb288a0SMasahiro Yamada #if !USE_COHERENT_MEM
1009fb288a0SMasahiro Yamada #define BAKERY_LOCK_NORMAL				\
1019fb288a0SMasahiro Yamada 	. = ALIGN(CACHE_WRITEBACK_GRANULE);		\
1029fb288a0SMasahiro Yamada 	__BAKERY_LOCK_START__ = .;			\
1039fb288a0SMasahiro Yamada 	__PERCPU_BAKERY_LOCK_START__ = .;		\
1049fb288a0SMasahiro Yamada 	*(bakery_lock)					\
1059fb288a0SMasahiro Yamada 	. = ALIGN(CACHE_WRITEBACK_GRANULE);		\
1069fb288a0SMasahiro Yamada 	__PERCPU_BAKERY_LOCK_END__ = .;			\
1079fb288a0SMasahiro Yamada 	__PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); \
1089fb288a0SMasahiro Yamada 	. = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \
1099fb288a0SMasahiro Yamada 	__BAKERY_LOCK_END__ = .;			\
1109fb288a0SMasahiro Yamada 	BAKERY_LOCK_SIZE_CHECK
1119fb288a0SMasahiro Yamada #else
1129fb288a0SMasahiro Yamada #define BAKERY_LOCK_NORMAL
1139fb288a0SMasahiro Yamada #endif
1149fb288a0SMasahiro Yamada 
1159fb288a0SMasahiro Yamada /*
1169fb288a0SMasahiro Yamada  * Time-stamps are stored in normal .bss memory
1179fb288a0SMasahiro Yamada  *
1189fb288a0SMasahiro Yamada  * The compiler will allocate enough memory for one CPU's time-stamps,
1199fb288a0SMasahiro Yamada  * the remaining memory for other CPUs is allocated by the
1209fb288a0SMasahiro Yamada  * linker script
1219fb288a0SMasahiro Yamada  */
1229fb288a0SMasahiro Yamada #define PMF_TIMESTAMP					\
1239fb288a0SMasahiro Yamada 	. = ALIGN(CACHE_WRITEBACK_GRANULE);		\
1249fb288a0SMasahiro Yamada 	__PMF_TIMESTAMP_START__ = .;			\
1259fb288a0SMasahiro Yamada 	KEEP(*(pmf_timestamp_array))			\
1269fb288a0SMasahiro Yamada 	. = ALIGN(CACHE_WRITEBACK_GRANULE);		\
1279fb288a0SMasahiro Yamada 	__PMF_PERCPU_TIMESTAMP_END__ = .;		\
1289fb288a0SMasahiro Yamada 	__PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); \
1299fb288a0SMasahiro Yamada 	. = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \
1309fb288a0SMasahiro Yamada 	__PMF_TIMESTAMP_END__ = .;
1319fb288a0SMasahiro Yamada 
132*a7739bc7SMasahiro Yamada 
133*a7739bc7SMasahiro Yamada /*
134*a7739bc7SMasahiro Yamada  * The .bss section gets initialised to 0 at runtime.
135*a7739bc7SMasahiro Yamada  * Its base address has bigger alignment for better performance of the
136*a7739bc7SMasahiro Yamada  * zero-initialization code.
137*a7739bc7SMasahiro Yamada  */
138*a7739bc7SMasahiro Yamada #define BSS_SECTION					\
139*a7739bc7SMasahiro Yamada 	.bss (NOLOAD) : ALIGN(BSS_ALIGN) {		\
140*a7739bc7SMasahiro Yamada 		__BSS_START__ = .;			\
141*a7739bc7SMasahiro Yamada 		*(SORT_BY_ALIGNMENT(.bss*))		\
142*a7739bc7SMasahiro Yamada 		*(COMMON)				\
143*a7739bc7SMasahiro Yamada 		BAKERY_LOCK_NORMAL			\
144*a7739bc7SMasahiro Yamada 		PMF_TIMESTAMP				\
145*a7739bc7SMasahiro Yamada 		__BSS_END__ = .;			\
146*a7739bc7SMasahiro Yamada 	}
147*a7739bc7SMasahiro Yamada 
148665e71b8SMasahiro Yamada /*
149665e71b8SMasahiro Yamada  * The xlat_table section is for full, aligned page tables (4K).
150665e71b8SMasahiro Yamada  * Removing them from .bss avoids forcing 4K alignment on
151665e71b8SMasahiro Yamada  * the .bss section. The tables are initialized to zero by the translation
152665e71b8SMasahiro Yamada  * tables library.
153665e71b8SMasahiro Yamada  */
154665e71b8SMasahiro Yamada #define XLAT_TABLE_SECTION				\
155665e71b8SMasahiro Yamada 	xlat_table (NOLOAD) : {				\
156665e71b8SMasahiro Yamada 		*(xlat_table)				\
157665e71b8SMasahiro Yamada 	}
158665e71b8SMasahiro Yamada 
159665e71b8SMasahiro Yamada #endif /* BL_COMMON_LD_H */
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