1665e71b8SMasahiro Yamada /* 2665e71b8SMasahiro Yamada * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3665e71b8SMasahiro Yamada * 4665e71b8SMasahiro Yamada * SPDX-License-Identifier: BSD-3-Clause 5665e71b8SMasahiro Yamada */ 6665e71b8SMasahiro Yamada 7665e71b8SMasahiro Yamada #ifndef BL_COMMON_LD_H 8665e71b8SMasahiro Yamada #define BL_COMMON_LD_H 9665e71b8SMasahiro Yamada 109fb288a0SMasahiro Yamada #include <platform_def.h> 119fb288a0SMasahiro Yamada 129fb288a0SMasahiro Yamada #ifdef __aarch64__ 139fb288a0SMasahiro Yamada #define STRUCT_ALIGN 8 14a7739bc7SMasahiro Yamada #define BSS_ALIGN 16 159fb288a0SMasahiro Yamada #else 169fb288a0SMasahiro Yamada #define STRUCT_ALIGN 4 17a7739bc7SMasahiro Yamada #define BSS_ALIGN 8 189fb288a0SMasahiro Yamada #endif 199fb288a0SMasahiro Yamada 209fb288a0SMasahiro Yamada #define CPU_OPS \ 219fb288a0SMasahiro Yamada . = ALIGN(STRUCT_ALIGN); \ 229fb288a0SMasahiro Yamada __CPU_OPS_START__ = .; \ 239fb288a0SMasahiro Yamada KEEP(*(cpu_ops)) \ 249fb288a0SMasahiro Yamada __CPU_OPS_END__ = .; 259fb288a0SMasahiro Yamada 269fb288a0SMasahiro Yamada #define PARSER_LIB_DESCS \ 279fb288a0SMasahiro Yamada . = ALIGN(STRUCT_ALIGN); \ 289fb288a0SMasahiro Yamada __PARSER_LIB_DESCS_START__ = .; \ 299fb288a0SMasahiro Yamada KEEP(*(.img_parser_lib_descs)) \ 309fb288a0SMasahiro Yamada __PARSER_LIB_DESCS_END__ = .; 319fb288a0SMasahiro Yamada 329fb288a0SMasahiro Yamada #define RT_SVC_DESCS \ 339fb288a0SMasahiro Yamada . = ALIGN(STRUCT_ALIGN); \ 349fb288a0SMasahiro Yamada __RT_SVC_DESCS_START__ = .; \ 359fb288a0SMasahiro Yamada KEEP(*(rt_svc_descs)) \ 369fb288a0SMasahiro Yamada __RT_SVC_DESCS_END__ = .; 379fb288a0SMasahiro Yamada 389fb288a0SMasahiro Yamada #define PMF_SVC_DESCS \ 399fb288a0SMasahiro Yamada . = ALIGN(STRUCT_ALIGN); \ 409fb288a0SMasahiro Yamada __PMF_SVC_DESCS_START__ = .; \ 419fb288a0SMasahiro Yamada KEEP(*(pmf_svc_descs)) \ 429fb288a0SMasahiro Yamada __PMF_SVC_DESCS_END__ = .; 439fb288a0SMasahiro Yamada 449fb288a0SMasahiro Yamada #define FCONF_POPULATOR \ 459fb288a0SMasahiro Yamada . = ALIGN(STRUCT_ALIGN); \ 469fb288a0SMasahiro Yamada __FCONF_POPULATOR_START__ = .; \ 479fb288a0SMasahiro Yamada KEEP(*(.fconf_populator)) \ 489fb288a0SMasahiro Yamada __FCONF_POPULATOR_END__ = .; 499fb288a0SMasahiro Yamada 509fb288a0SMasahiro Yamada /* 519fb288a0SMasahiro Yamada * Keep the .got section in the RO section as it is patched prior to enabling 529fb288a0SMasahiro Yamada * the MMU and having the .got in RO is better for security. GOT is a table of 539fb288a0SMasahiro Yamada * addresses so ensure pointer size alignment. 549fb288a0SMasahiro Yamada */ 559fb288a0SMasahiro Yamada #define GOT \ 569fb288a0SMasahiro Yamada . = ALIGN(STRUCT_ALIGN); \ 579fb288a0SMasahiro Yamada __GOT_START__ = .; \ 589fb288a0SMasahiro Yamada *(.got) \ 599fb288a0SMasahiro Yamada __GOT_END__ = .; 609fb288a0SMasahiro Yamada 61*268131c2SMasahiro Yamada /* 62*268131c2SMasahiro Yamada * The base xlat table 63*268131c2SMasahiro Yamada * 64*268131c2SMasahiro Yamada * It is put into the rodata section if PLAT_RO_XLAT_TABLES=1, 65*268131c2SMasahiro Yamada * or into the bss section otherwise. 66*268131c2SMasahiro Yamada */ 67*268131c2SMasahiro Yamada #define BASE_XLAT_TABLE \ 68*268131c2SMasahiro Yamada . = ALIGN(16); \ 69*268131c2SMasahiro Yamada *(base_xlat_table) 70*268131c2SMasahiro Yamada 71*268131c2SMasahiro Yamada #if PLAT_RO_XLAT_TABLES 72*268131c2SMasahiro Yamada #define BASE_XLAT_TABLE_RO BASE_XLAT_TABLE 73*268131c2SMasahiro Yamada #define BASE_XLAT_TABLE_BSS 74*268131c2SMasahiro Yamada #else 75*268131c2SMasahiro Yamada #define BASE_XLAT_TABLE_RO 76*268131c2SMasahiro Yamada #define BASE_XLAT_TABLE_BSS BASE_XLAT_TABLE 77*268131c2SMasahiro Yamada #endif 78*268131c2SMasahiro Yamada 790a0a7a9aSMasahiro Yamada #define RODATA_COMMON \ 800a0a7a9aSMasahiro Yamada RT_SVC_DESCS \ 810a0a7a9aSMasahiro Yamada FCONF_POPULATOR \ 820a0a7a9aSMasahiro Yamada PMF_SVC_DESCS \ 830a0a7a9aSMasahiro Yamada PARSER_LIB_DESCS \ 840a0a7a9aSMasahiro Yamada CPU_OPS \ 85*268131c2SMasahiro Yamada GOT \ 86*268131c2SMasahiro Yamada BASE_XLAT_TABLE_RO 870a0a7a9aSMasahiro Yamada 889fb288a0SMasahiro Yamada #define STACK_SECTION \ 899fb288a0SMasahiro Yamada stacks (NOLOAD) : { \ 909fb288a0SMasahiro Yamada __STACKS_START__ = .; \ 919fb288a0SMasahiro Yamada *(tzfw_normal_stacks) \ 929fb288a0SMasahiro Yamada __STACKS_END__ = .; \ 939fb288a0SMasahiro Yamada } 949fb288a0SMasahiro Yamada 959fb288a0SMasahiro Yamada /* 969fb288a0SMasahiro Yamada * If BL doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__ 979fb288a0SMasahiro Yamada * will be zero. For this reason, the only two valid values for 989fb288a0SMasahiro Yamada * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value 999fb288a0SMasahiro Yamada * PLAT_PERCPU_BAKERY_LOCK_SIZE. 1009fb288a0SMasahiro Yamada */ 1019fb288a0SMasahiro Yamada #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 1029fb288a0SMasahiro Yamada #define BAKERY_LOCK_SIZE_CHECK \ 1039fb288a0SMasahiro Yamada ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || \ 1049fb288a0SMasahiro Yamada (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE), \ 1059fb288a0SMasahiro Yamada "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 1069fb288a0SMasahiro Yamada #else 1079fb288a0SMasahiro Yamada #define BAKERY_LOCK_SIZE_CHECK 1089fb288a0SMasahiro Yamada #endif 1099fb288a0SMasahiro Yamada 1109fb288a0SMasahiro Yamada /* 1119fb288a0SMasahiro Yamada * Bakery locks are stored in normal .bss memory 1129fb288a0SMasahiro Yamada * 1139fb288a0SMasahiro Yamada * Each lock's data is spread across multiple cache lines, one per CPU, 1149fb288a0SMasahiro Yamada * but multiple locks can share the same cache line. 1159fb288a0SMasahiro Yamada * The compiler will allocate enough memory for one CPU's bakery locks, 1169fb288a0SMasahiro Yamada * the remaining cache lines are allocated by the linker script 1179fb288a0SMasahiro Yamada */ 1189fb288a0SMasahiro Yamada #if !USE_COHERENT_MEM 1199fb288a0SMasahiro Yamada #define BAKERY_LOCK_NORMAL \ 1209fb288a0SMasahiro Yamada . = ALIGN(CACHE_WRITEBACK_GRANULE); \ 1219fb288a0SMasahiro Yamada __BAKERY_LOCK_START__ = .; \ 1229fb288a0SMasahiro Yamada __PERCPU_BAKERY_LOCK_START__ = .; \ 1239fb288a0SMasahiro Yamada *(bakery_lock) \ 1249fb288a0SMasahiro Yamada . = ALIGN(CACHE_WRITEBACK_GRANULE); \ 1259fb288a0SMasahiro Yamada __PERCPU_BAKERY_LOCK_END__ = .; \ 1269fb288a0SMasahiro Yamada __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); \ 1279fb288a0SMasahiro Yamada . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \ 1289fb288a0SMasahiro Yamada __BAKERY_LOCK_END__ = .; \ 1299fb288a0SMasahiro Yamada BAKERY_LOCK_SIZE_CHECK 1309fb288a0SMasahiro Yamada #else 1319fb288a0SMasahiro Yamada #define BAKERY_LOCK_NORMAL 1329fb288a0SMasahiro Yamada #endif 1339fb288a0SMasahiro Yamada 1349fb288a0SMasahiro Yamada /* 1359fb288a0SMasahiro Yamada * Time-stamps are stored in normal .bss memory 1369fb288a0SMasahiro Yamada * 1379fb288a0SMasahiro Yamada * The compiler will allocate enough memory for one CPU's time-stamps, 1389fb288a0SMasahiro Yamada * the remaining memory for other CPUs is allocated by the 1399fb288a0SMasahiro Yamada * linker script 1409fb288a0SMasahiro Yamada */ 1419fb288a0SMasahiro Yamada #define PMF_TIMESTAMP \ 1429fb288a0SMasahiro Yamada . = ALIGN(CACHE_WRITEBACK_GRANULE); \ 1439fb288a0SMasahiro Yamada __PMF_TIMESTAMP_START__ = .; \ 1449fb288a0SMasahiro Yamada KEEP(*(pmf_timestamp_array)) \ 1459fb288a0SMasahiro Yamada . = ALIGN(CACHE_WRITEBACK_GRANULE); \ 1469fb288a0SMasahiro Yamada __PMF_PERCPU_TIMESTAMP_END__ = .; \ 1479fb288a0SMasahiro Yamada __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); \ 1489fb288a0SMasahiro Yamada . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \ 1499fb288a0SMasahiro Yamada __PMF_TIMESTAMP_END__ = .; 1509fb288a0SMasahiro Yamada 151a7739bc7SMasahiro Yamada 152a7739bc7SMasahiro Yamada /* 153a7739bc7SMasahiro Yamada * The .bss section gets initialised to 0 at runtime. 154a7739bc7SMasahiro Yamada * Its base address has bigger alignment for better performance of the 155a7739bc7SMasahiro Yamada * zero-initialization code. 156a7739bc7SMasahiro Yamada */ 157a7739bc7SMasahiro Yamada #define BSS_SECTION \ 158a7739bc7SMasahiro Yamada .bss (NOLOAD) : ALIGN(BSS_ALIGN) { \ 159a7739bc7SMasahiro Yamada __BSS_START__ = .; \ 160a7739bc7SMasahiro Yamada *(SORT_BY_ALIGNMENT(.bss*)) \ 161a7739bc7SMasahiro Yamada *(COMMON) \ 162a7739bc7SMasahiro Yamada BAKERY_LOCK_NORMAL \ 163a7739bc7SMasahiro Yamada PMF_TIMESTAMP \ 164*268131c2SMasahiro Yamada BASE_XLAT_TABLE_BSS \ 165a7739bc7SMasahiro Yamada __BSS_END__ = .; \ 166a7739bc7SMasahiro Yamada } 167a7739bc7SMasahiro Yamada 168665e71b8SMasahiro Yamada /* 169665e71b8SMasahiro Yamada * The xlat_table section is for full, aligned page tables (4K). 170665e71b8SMasahiro Yamada * Removing them from .bss avoids forcing 4K alignment on 171665e71b8SMasahiro Yamada * the .bss section. The tables are initialized to zero by the translation 172665e71b8SMasahiro Yamada * tables library. 173665e71b8SMasahiro Yamada */ 174665e71b8SMasahiro Yamada #define XLAT_TABLE_SECTION \ 175665e71b8SMasahiro Yamada xlat_table (NOLOAD) : { \ 176665e71b8SMasahiro Yamada *(xlat_table) \ 177665e71b8SMasahiro Yamada } 178665e71b8SMasahiro Yamada 179665e71b8SMasahiro Yamada #endif /* BL_COMMON_LD_H */ 180