1 /* 2 * Copyright (c) 2022, ARM Limited. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef TRAP_HANDLE_H 9 #define TRAP_HANDLE_H 10 11 #include <stdbool.h> 12 #include <context.h> 13 14 #define ISS_SYSREG_OPCODE_MASK 0x3ffc1eUL 15 #define ISS_IDREG_OPCODE_MASK 0x31bc00UL 16 #define ISS_SYSREG_REG_MASK 0x0003e0UL 17 #define ISS_SYSREG_REG_SHIFT 5U 18 #define ISS_SYSREG_DIRECTION_MASK 0x000001UL 19 20 #define ISS_SYSREG_OPCODE_RNDR 0x30c808U 21 #define ISS_SYSREG_OPCODE_IMPDEF 0x303c00U 22 #define ISS_SYSREG_OPCODE_RNDRRS 0x32c808U 23 #define ISS_SYSREG_OPCODE_IDREG 0x300000U 24 25 #define TRAP_RET_UNHANDLED -1 26 #define TRAP_RET_REPEAT 0 27 #define TRAP_RET_CONTINUE 1 28 29 #ifndef __ASSEMBLER__ 30 static inline unsigned int get_sysreg_iss_rt(uint64_t esr) 31 { 32 return (esr & ISS_SYSREG_REG_MASK) >> ISS_SYSREG_REG_SHIFT; 33 } 34 35 static inline bool is_sysreg_iss_write(uint64_t esr) 36 { 37 return !(esr & ISS_SYSREG_DIRECTION_MASK); 38 } 39 40 /** 41 * handle_sysreg_trap() - Handle AArch64 system register traps from lower ELs 42 * @esr_el3: The content of ESR_EL3, containing the trap syndrome information 43 * @ctx: Pointer to the lower EL context, containing saved registers 44 * 45 * Called by the exception handler when a synchronous trap identifies as a 46 * system register trap (EC=0x18). ESR contains the encoding of the op[x] and 47 * CRm/CRn fields, to identify the system register, and the target/source 48 * GPR plus the direction (MRS/MSR). The lower EL's context can be altered 49 * by the function, to inject back the result of the emulation. 50 * 51 * Return: indication how to proceed with the trap: 52 * TRAP_RET_UNHANDLED(-1): trap is unhandled, trigger panic 53 * TRAP_RET_REPEAT(0): trap was handled, return to the trapping instruction 54 * (repeating it) 55 * TRAP_RET_CONTINUE(1): trap was handled, return to the next instruction 56 * (continuing after it) 57 */ 58 int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx, 59 u_register_t flags __unused); 60 61 /* Handler for injecting UNDEF exception to lower EL */ 62 void inject_undef64(cpu_context_t *ctx); 63 64 u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el); 65 66 /* Prototypes for system register emulation handlers provided by platforms. */ 67 int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx); 68 int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx); 69 70 #endif /* __ASSEMBLER__ */ 71 72 #endif 73