xref: /rk3399_ARM-atf/include/bl31/interrupt_mgmt.h (revision c6bc071020baebc660fc94390b50bc240e34c0a3)
1e1333f75SAchin Gupta /*
2e1333f75SAchin Gupta  * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3e1333f75SAchin Gupta  *
4e1333f75SAchin Gupta  * Redistribution and use in source and binary forms, with or without
5e1333f75SAchin Gupta  * modification, are permitted provided that the following conditions are met:
6e1333f75SAchin Gupta  *
7e1333f75SAchin Gupta  * Redistributions of source code must retain the above copyright notice, this
8e1333f75SAchin Gupta  * list of conditions and the following disclaimer.
9e1333f75SAchin Gupta  *
10e1333f75SAchin Gupta  * Redistributions in binary form must reproduce the above copyright notice,
11e1333f75SAchin Gupta  * this list of conditions and the following disclaimer in the documentation
12e1333f75SAchin Gupta  * and/or other materials provided with the distribution.
13e1333f75SAchin Gupta  *
14e1333f75SAchin Gupta  * Neither the name of ARM nor the names of its contributors may be used
15e1333f75SAchin Gupta  * to endorse or promote products derived from this software without specific
16e1333f75SAchin Gupta  * prior written permission.
17e1333f75SAchin Gupta  *
18e1333f75SAchin Gupta  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19e1333f75SAchin Gupta  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20e1333f75SAchin Gupta  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21e1333f75SAchin Gupta  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22e1333f75SAchin Gupta  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23e1333f75SAchin Gupta  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24e1333f75SAchin Gupta  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25e1333f75SAchin Gupta  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26e1333f75SAchin Gupta  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27e1333f75SAchin Gupta  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28e1333f75SAchin Gupta  * POSSIBILITY OF SUCH DAMAGE.
29e1333f75SAchin Gupta  */
30e1333f75SAchin Gupta 
31e1333f75SAchin Gupta #ifndef __INTERRUPT_MGMT_H__
32e1333f75SAchin Gupta #define __INTERRUPT_MGMT_H__
33e1333f75SAchin Gupta 
34e1333f75SAchin Gupta #include <arch.h>
35e1333f75SAchin Gupta 
36e1333f75SAchin Gupta /*******************************************************************************
37e1333f75SAchin Gupta  * Constants for the types of interrupts recognised by the IM framework
38e1333f75SAchin Gupta  ******************************************************************************/
39e1333f75SAchin Gupta #define INTR_TYPE_S_EL1			0
40e1333f75SAchin Gupta #define INTR_TYPE_EL3			1
41e1333f75SAchin Gupta #define INTR_TYPE_NS			2
42e1333f75SAchin Gupta #define MAX_INTR_TYPES			3
43e1333f75SAchin Gupta #define INTR_TYPE_INVAL			MAX_INTR_TYPES
44e1333f75SAchin Gupta /*
45e1333f75SAchin Gupta  * Constant passed to the interrupt handler in the 'id' field when the
46e1333f75SAchin Gupta  * framework does not read the gic registers to determine the interrupt id.
47e1333f75SAchin Gupta  */
48e1333f75SAchin Gupta #define INTR_ID_UNAVAILABLE		0xFFFFFFFF
49e1333f75SAchin Gupta 
50e1333f75SAchin Gupta 
51e1333f75SAchin Gupta /*******************************************************************************
52e1333f75SAchin Gupta  * Mask for _both_ the routing model bits in the 'flags' parameter and
53e1333f75SAchin Gupta  * constants to define the valid routing models for each supported interrupt
54e1333f75SAchin Gupta  * type
55e1333f75SAchin Gupta  ******************************************************************************/
56e1333f75SAchin Gupta #define INTR_RM_FLAGS_SHIFT		0x0
57e1333f75SAchin Gupta #define INTR_RM_FLAGS_MASK		0x3
58e1333f75SAchin Gupta /* Routed to EL3 from NS. Taken to S-EL1 from Secure */
59e1333f75SAchin Gupta #define INTR_SEL1_VALID_RM0		0x2
60e1333f75SAchin Gupta /* Routed to EL3 from NS and Secure */
61e1333f75SAchin Gupta #define INTR_SEL1_VALID_RM1		0x3
62e1333f75SAchin Gupta /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */
63e1333f75SAchin Gupta #define INTR_NS_VALID_RM0		0x0
64e1333f75SAchin Gupta /* Routed to EL1/EL2 from NS and to EL3 from Secure */
65e1333f75SAchin Gupta #define INTR_NS_VALID_RM1		0x1
66e1333f75SAchin Gupta 
67e1333f75SAchin Gupta 
68e1333f75SAchin Gupta /*******************************************************************************
69e1333f75SAchin Gupta  * Constants for the _individual_ routing model bits in the 'flags' field for
70e1333f75SAchin Gupta  * each interrupt type and mask to validate the 'flags' parameter while
71e1333f75SAchin Gupta  * registering an interrupt handler
72e1333f75SAchin Gupta  ******************************************************************************/
73e1333f75SAchin Gupta #define INTR_TYPE_FLAGS_MASK		0xFFFFFFFC
74e1333f75SAchin Gupta 
75e1333f75SAchin Gupta #define INTR_RM_FROM_SEC_SHIFT		SECURE		/* BIT[0] */
76e1333f75SAchin Gupta #define INTR_RM_FROM_NS_SHIFT		NON_SECURE	/* BIT[1] */
77e1333f75SAchin Gupta #define INTR_RM_FROM_FLAG_MASK		1
78e1333f75SAchin Gupta #define get_interrupt_rm_flag(flag, ss)	(((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \
79e1333f75SAchin Gupta 					 & INTR_RM_FROM_FLAG_MASK)
80e1333f75SAchin Gupta #define set_interrupt_rm_flag(flag, ss)	(flag |= 1 << ss)
81e1333f75SAchin Gupta #define clr_interrupt_rm_flag(flag, ss)	(flag &= ~(1 << ss))
82e1333f75SAchin Gupta 
83e1333f75SAchin Gupta 
84e1333f75SAchin Gupta /*******************************************************************************
85e1333f75SAchin Gupta  * Macros to validate the routing model bits in the 'flags' for a type
86e1333f75SAchin Gupta  * of interrupt. If the model does not match one of the valid masks
87e1333f75SAchin Gupta  * -EINVAL is returned.
88e1333f75SAchin Gupta  ******************************************************************************/
89e1333f75SAchin Gupta #define validate_sel1_interrupt_rm(x)	(x == INTR_SEL1_VALID_RM0 ? 0 : \
90e1333f75SAchin Gupta 					 (x == INTR_SEL1_VALID_RM1 ? 0 :\
91e1333f75SAchin Gupta 					  -EINVAL))
92e1333f75SAchin Gupta 
93e1333f75SAchin Gupta #define validate_ns_interrupt_rm(x)	(x == INTR_NS_VALID_RM0 ? 0 : \
94e1333f75SAchin Gupta 					 (x == INTR_NS_VALID_RM1 ? 0 :\
95e1333f75SAchin Gupta 					  -EINVAL))
96e1333f75SAchin Gupta 
97e1333f75SAchin Gupta /*******************************************************************************
98e1333f75SAchin Gupta  * Macros to set the 'flags' parameter passed to an interrupt type handler. Only
99e1333f75SAchin Gupta  * the flag to indicate the security state when the exception was generated is
100e1333f75SAchin Gupta  * supported.
101e1333f75SAchin Gupta  ******************************************************************************/
102e1333f75SAchin Gupta #define INTR_SRC_SS_FLAG_SHIFT		0		/* BIT[0] */
103e1333f75SAchin Gupta #define INTR_SRC_SS_FLAG_MASK		1
104e1333f75SAchin Gupta #define set_interrupt_src_ss(flag, val)	(flag |= val << INTR_SRC_SS_FLAG_SHIFT)
105e1333f75SAchin Gupta #define clr_interrupt_src_ss(flag)	(flag &= ~(1 << INTR_SRC_SS_FLAG_SHIFT))
106e1333f75SAchin Gupta #define get_interrupt_src_ss(flag)	((flag >> INTR_SRC_SS_FLAG_SHIFT) & \
107e1333f75SAchin Gupta 					 INTR_SRC_SS_FLAG_MASK)
108e1333f75SAchin Gupta 
109e1333f75SAchin Gupta #ifndef __ASSEMBLY__
110e1333f75SAchin Gupta 
111e1333f75SAchin Gupta /* Prototype for defining a handler for an interrupt type */
112e1333f75SAchin Gupta typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
113e1333f75SAchin Gupta 					     uint32_t flags,
114e1333f75SAchin Gupta 					     void *handle,
115e1333f75SAchin Gupta 					     void *cookie);
116e1333f75SAchin Gupta 
117e1333f75SAchin Gupta /*******************************************************************************
118e1333f75SAchin Gupta  * Function & variable prototypes
119e1333f75SAchin Gupta  ******************************************************************************/
120*c6bc0710SDan Handley uint32_t get_scr_el3_from_routing_model(uint32_t security_state);
121*c6bc0710SDan Handley int32_t set_routing_model(uint32_t type, uint32_t flags);
122*c6bc0710SDan Handley int32_t register_interrupt_type_handler(uint32_t type,
123e1333f75SAchin Gupta 					interrupt_type_handler_t handler,
124e1333f75SAchin Gupta 					uint32_t flags);
125*c6bc0710SDan Handley interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type);
126e1333f75SAchin Gupta 
127e1333f75SAchin Gupta #endif /*__ASSEMBLY__*/
128e1333f75SAchin Gupta #endif /* __INTERRUPT_MGMT_H__ */
129