1e1333f75SAchin Gupta /* 2fc529feeSJeenu Viswambharan * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3e1333f75SAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5e1333f75SAchin Gupta */ 6e1333f75SAchin Gupta 7e1333f75SAchin Gupta #ifndef __INTERRUPT_MGMT_H__ 8e1333f75SAchin Gupta #define __INTERRUPT_MGMT_H__ 9e1333f75SAchin Gupta 10e1333f75SAchin Gupta #include <arch.h> 11e1333f75SAchin Gupta 12e1333f75SAchin Gupta /******************************************************************************* 13e1333f75SAchin Gupta * Constants for the types of interrupts recognised by the IM framework 14e1333f75SAchin Gupta ******************************************************************************/ 15030567e6SVarun Wadekar #define INTR_TYPE_S_EL1 U(0) 16030567e6SVarun Wadekar #define INTR_TYPE_EL3 U(1) 17030567e6SVarun Wadekar #define INTR_TYPE_NS U(2) 18030567e6SVarun Wadekar #define MAX_INTR_TYPES U(3) 19e1333f75SAchin Gupta #define INTR_TYPE_INVAL MAX_INTR_TYPES 20fc529feeSJeenu Viswambharan 21fc529feeSJeenu Viswambharan /* Interrupt routing modes */ 22fc529feeSJeenu Viswambharan #define INTR_ROUTING_MODE_PE 0 23fc529feeSJeenu Viswambharan #define INTR_ROUTING_MODE_ANY 1 24fc529feeSJeenu Viswambharan 25e1333f75SAchin Gupta /* 26e1333f75SAchin Gupta * Constant passed to the interrupt handler in the 'id' field when the 27e1333f75SAchin Gupta * framework does not read the gic registers to determine the interrupt id. 28e1333f75SAchin Gupta */ 29030567e6SVarun Wadekar #define INTR_ID_UNAVAILABLE U(0xFFFFFFFF) 30e1333f75SAchin Gupta 31e1333f75SAchin Gupta 32e1333f75SAchin Gupta /******************************************************************************* 33e1333f75SAchin Gupta * Mask for _both_ the routing model bits in the 'flags' parameter and 34e1333f75SAchin Gupta * constants to define the valid routing models for each supported interrupt 35e1333f75SAchin Gupta * type 36e1333f75SAchin Gupta ******************************************************************************/ 37030567e6SVarun Wadekar #define INTR_RM_FLAGS_SHIFT U(0x0) 38030567e6SVarun Wadekar #define INTR_RM_FLAGS_MASK U(0x3) 39e1333f75SAchin Gupta /* Routed to EL3 from NS. Taken to S-EL1 from Secure */ 40030567e6SVarun Wadekar #define INTR_SEL1_VALID_RM0 U(0x2) 41e1333f75SAchin Gupta /* Routed to EL3 from NS and Secure */ 42030567e6SVarun Wadekar #define INTR_SEL1_VALID_RM1 U(0x3) 43e1333f75SAchin Gupta /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ 44030567e6SVarun Wadekar #define INTR_NS_VALID_RM0 U(0x0) 45e1333f75SAchin Gupta /* Routed to EL1/EL2 from NS and to EL3 from Secure */ 46030567e6SVarun Wadekar #define INTR_NS_VALID_RM1 U(0x1) 474e0e0f44SSoby Mathew /* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */ 48030567e6SVarun Wadekar #define INTR_EL3_VALID_RM0 U(0x2) 494e0e0f44SSoby Mathew /* Routed to EL3 from NS and Secure */ 50030567e6SVarun Wadekar #define INTR_EL3_VALID_RM1 U(0x3) 51f4f1ae77SSoby Mathew /* This is the default routing model */ 52030567e6SVarun Wadekar #define INTR_DEFAULT_RM U(0x0) 53e1333f75SAchin Gupta 54e1333f75SAchin Gupta /******************************************************************************* 55e1333f75SAchin Gupta * Constants for the _individual_ routing model bits in the 'flags' field for 56e1333f75SAchin Gupta * each interrupt type and mask to validate the 'flags' parameter while 57e1333f75SAchin Gupta * registering an interrupt handler 58e1333f75SAchin Gupta ******************************************************************************/ 59030567e6SVarun Wadekar #define INTR_TYPE_FLAGS_MASK U(0xFFFFFFFC) 60e1333f75SAchin Gupta 61e1333f75SAchin Gupta #define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ 62e1333f75SAchin Gupta #define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ 63030567e6SVarun Wadekar #define INTR_RM_FROM_FLAG_MASK U(1) 64e1333f75SAchin Gupta #define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ 65e1333f75SAchin Gupta & INTR_RM_FROM_FLAG_MASK) 66030567e6SVarun Wadekar #define set_interrupt_rm_flag(flag, ss) (flag |= U(1) << ss) 67030567e6SVarun Wadekar #define clr_interrupt_rm_flag(flag, ss) (flag &= ~(U(1) << ss)) 68e1333f75SAchin Gupta 69e1333f75SAchin Gupta 70e1333f75SAchin Gupta /******************************************************************************* 71e1333f75SAchin Gupta * Macros to validate the routing model bits in the 'flags' for a type 72e1333f75SAchin Gupta * of interrupt. If the model does not match one of the valid masks 73e1333f75SAchin Gupta * -EINVAL is returned. 74e1333f75SAchin Gupta ******************************************************************************/ 754e0e0f44SSoby Mathew #define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \ 764e0e0f44SSoby Mathew ((x) == INTR_SEL1_VALID_RM1 ? 0 :\ 77e1333f75SAchin Gupta -EINVAL)) 78e1333f75SAchin Gupta 794e0e0f44SSoby Mathew #define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \ 804e0e0f44SSoby Mathew ((x) == INTR_NS_VALID_RM1 ? 0 :\ 814e0e0f44SSoby Mathew -EINVAL)) 824e0e0f44SSoby Mathew 834e0e0f44SSoby Mathew #define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \ 844e0e0f44SSoby Mathew ((x) == INTR_EL3_VALID_RM1 ? 0 :\ 85e1333f75SAchin Gupta -EINVAL)) 86e1333f75SAchin Gupta 87e1333f75SAchin Gupta /******************************************************************************* 88e1333f75SAchin Gupta * Macros to set the 'flags' parameter passed to an interrupt type handler. Only 89e1333f75SAchin Gupta * the flag to indicate the security state when the exception was generated is 90e1333f75SAchin Gupta * supported. 91e1333f75SAchin Gupta ******************************************************************************/ 92030567e6SVarun Wadekar #define INTR_SRC_SS_FLAG_SHIFT U(0) /* BIT[0] */ 93030567e6SVarun Wadekar #define INTR_SRC_SS_FLAG_MASK U(1) 94e1333f75SAchin Gupta #define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) 95030567e6SVarun Wadekar #define clr_interrupt_src_ss(flag) (flag &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT)) 96e1333f75SAchin Gupta #define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ 97e1333f75SAchin Gupta INTR_SRC_SS_FLAG_MASK) 98e1333f75SAchin Gupta 99e1333f75SAchin Gupta #ifndef __ASSEMBLY__ 100e1333f75SAchin Gupta 101*c639e8ebSJeenu Viswambharan #include <stdint.h> 102*c639e8ebSJeenu Viswambharan 103e1333f75SAchin Gupta /* Prototype for defining a handler for an interrupt type */ 104e1333f75SAchin Gupta typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, 105e1333f75SAchin Gupta uint32_t flags, 106e1333f75SAchin Gupta void *handle, 107e1333f75SAchin Gupta void *cookie); 108e1333f75SAchin Gupta 109e1333f75SAchin Gupta /******************************************************************************* 110e1333f75SAchin Gupta * Function & variable prototypes 111e1333f75SAchin Gupta ******************************************************************************/ 112c6bc0710SDan Handley uint32_t get_scr_el3_from_routing_model(uint32_t security_state); 113c6bc0710SDan Handley int32_t set_routing_model(uint32_t type, uint32_t flags); 114c6bc0710SDan Handley int32_t register_interrupt_type_handler(uint32_t type, 115e1333f75SAchin Gupta interrupt_type_handler_t handler, 116e1333f75SAchin Gupta uint32_t flags); 117c6bc0710SDan Handley interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type); 118f4f1ae77SSoby Mathew int disable_intr_rm_local(uint32_t type, uint32_t security_state); 119f4f1ae77SSoby Mathew int enable_intr_rm_local(uint32_t type, uint32_t security_state); 120e1333f75SAchin Gupta 121e1333f75SAchin Gupta #endif /*__ASSEMBLY__*/ 122e1333f75SAchin Gupta #endif /* __INTERRUPT_MGMT_H__ */ 123