xref: /rk3399_ARM-atf/include/bl31/interrupt_mgmt.h (revision 09d40e0e08283a249e7dce0e106c07c5141f9b7e)
1e1333f75SAchin Gupta /*
226ea3908SJeenu Viswambharan  * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
3e1333f75SAchin Gupta  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
5e1333f75SAchin Gupta  */
6e1333f75SAchin Gupta 
7c3cf06f1SAntonio Nino Diaz #ifndef INTERRUPT_MGMT_H
8c3cf06f1SAntonio Nino Diaz #define INTERRUPT_MGMT_H
9e1333f75SAchin Gupta 
10e1333f75SAchin Gupta #include <arch.h>
11*09d40e0eSAntonio Nino Diaz #include <lib/utils_def.h>
12e1333f75SAchin Gupta 
13e1333f75SAchin Gupta /*******************************************************************************
14e1333f75SAchin Gupta  * Constants for the types of interrupts recognised by the IM framework
15e1333f75SAchin Gupta  ******************************************************************************/
16030567e6SVarun Wadekar #define INTR_TYPE_S_EL1			U(0)
17030567e6SVarun Wadekar #define INTR_TYPE_EL3			U(1)
18030567e6SVarun Wadekar #define INTR_TYPE_NS			U(2)
19030567e6SVarun Wadekar #define MAX_INTR_TYPES			U(3)
20e1333f75SAchin Gupta #define INTR_TYPE_INVAL			MAX_INTR_TYPES
21fc529feeSJeenu Viswambharan 
22fc529feeSJeenu Viswambharan /* Interrupt routing modes */
23fc529feeSJeenu Viswambharan #define INTR_ROUTING_MODE_PE		0
24fc529feeSJeenu Viswambharan #define INTR_ROUTING_MODE_ANY		1
25fc529feeSJeenu Viswambharan 
26e1333f75SAchin Gupta /*
27e1333f75SAchin Gupta  * Constant passed to the interrupt handler in the 'id' field when the
28e1333f75SAchin Gupta  * framework does not read the gic registers to determine the interrupt id.
29e1333f75SAchin Gupta  */
30030567e6SVarun Wadekar #define INTR_ID_UNAVAILABLE		U(0xFFFFFFFF)
31e1333f75SAchin Gupta 
32e1333f75SAchin Gupta 
33e1333f75SAchin Gupta /*******************************************************************************
34e1333f75SAchin Gupta  * Mask for _both_ the routing model bits in the 'flags' parameter and
35e1333f75SAchin Gupta  * constants to define the valid routing models for each supported interrupt
36e1333f75SAchin Gupta  * type
37e1333f75SAchin Gupta  ******************************************************************************/
38030567e6SVarun Wadekar #define INTR_RM_FLAGS_SHIFT		U(0x0)
39030567e6SVarun Wadekar #define INTR_RM_FLAGS_MASK		U(0x3)
40e1333f75SAchin Gupta /* Routed to EL3 from NS. Taken to S-EL1 from Secure */
41030567e6SVarun Wadekar #define INTR_SEL1_VALID_RM0		U(0x2)
42e1333f75SAchin Gupta /* Routed to EL3 from NS and Secure */
43030567e6SVarun Wadekar #define INTR_SEL1_VALID_RM1		U(0x3)
44e1333f75SAchin Gupta /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */
45030567e6SVarun Wadekar #define INTR_NS_VALID_RM0		U(0x0)
46e1333f75SAchin Gupta /* Routed to EL1/EL2 from NS and to EL3 from Secure */
47030567e6SVarun Wadekar #define INTR_NS_VALID_RM1		U(0x1)
484e0e0f44SSoby Mathew /* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */
49030567e6SVarun Wadekar #define INTR_EL3_VALID_RM0		U(0x2)
504e0e0f44SSoby Mathew /* Routed to EL3 from NS and Secure */
51030567e6SVarun Wadekar #define INTR_EL3_VALID_RM1		U(0x3)
52f4f1ae77SSoby Mathew /* This is the default routing model */
53030567e6SVarun Wadekar #define INTR_DEFAULT_RM			U(0x0)
54e1333f75SAchin Gupta 
55e1333f75SAchin Gupta /*******************************************************************************
56e1333f75SAchin Gupta  * Constants for the _individual_ routing model bits in the 'flags' field for
57e1333f75SAchin Gupta  * each interrupt type and mask to validate the 'flags' parameter while
58e1333f75SAchin Gupta  * registering an interrupt handler
59e1333f75SAchin Gupta  ******************************************************************************/
60030567e6SVarun Wadekar #define INTR_TYPE_FLAGS_MASK		U(0xFFFFFFFC)
61e1333f75SAchin Gupta 
62e1333f75SAchin Gupta #define INTR_RM_FROM_SEC_SHIFT		SECURE		/* BIT[0] */
63e1333f75SAchin Gupta #define INTR_RM_FROM_NS_SHIFT		NON_SECURE	/* BIT[1] */
64030567e6SVarun Wadekar #define INTR_RM_FROM_FLAG_MASK		U(1)
6503b645edSJeenu Viswambharan #define get_interrupt_rm_flag(flag, ss) \
6603b645edSJeenu Viswambharan 	((((flag) >> INTR_RM_FLAGS_SHIFT) >> (ss)) & INTR_RM_FROM_FLAG_MASK)
6703b645edSJeenu Viswambharan #define set_interrupt_rm_flag(flag, ss)	((flag) |= U(1) << (ss))
6803b645edSJeenu Viswambharan #define clr_interrupt_rm_flag(flag, ss)	((flag) &= ~(U(1) << (ss)))
69e1333f75SAchin Gupta 
70e1333f75SAchin Gupta /*******************************************************************************
71e1333f75SAchin Gupta  * Macros to set the 'flags' parameter passed to an interrupt type handler. Only
72e1333f75SAchin Gupta  * the flag to indicate the security state when the exception was generated is
73e1333f75SAchin Gupta  * supported.
74e1333f75SAchin Gupta  ******************************************************************************/
75030567e6SVarun Wadekar #define INTR_SRC_SS_FLAG_SHIFT		U(0)		/* BIT[0] */
76030567e6SVarun Wadekar #define INTR_SRC_SS_FLAG_MASK		U(1)
77ba6e5ca6SJeenu Viswambharan #define set_interrupt_src_ss(flag, val)	((flag) |= (val) << INTR_SRC_SS_FLAG_SHIFT)
78ba6e5ca6SJeenu Viswambharan #define clr_interrupt_src_ss(flag)	((flag) &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT))
79ba6e5ca6SJeenu Viswambharan #define get_interrupt_src_ss(flag)	(((flag) >> INTR_SRC_SS_FLAG_SHIFT) & \
80e1333f75SAchin Gupta 					 INTR_SRC_SS_FLAG_MASK)
81e1333f75SAchin Gupta 
82e1333f75SAchin Gupta #ifndef __ASSEMBLY__
83e1333f75SAchin Gupta 
84c9512bcaSAntonio Nino Diaz #include <errno.h>
85c639e8ebSJeenu Viswambharan #include <stdint.h>
86c639e8ebSJeenu Viswambharan 
87c9512bcaSAntonio Nino Diaz /*******************************************************************************
88c9512bcaSAntonio Nino Diaz  * Helpers to validate the routing model bits in the 'flags' for a type
89c9512bcaSAntonio Nino Diaz  * of interrupt. If the model does not match one of the valid masks
90c9512bcaSAntonio Nino Diaz  * -EINVAL is returned.
91c9512bcaSAntonio Nino Diaz  ******************************************************************************/
92c9512bcaSAntonio Nino Diaz static inline int32_t validate_sel1_interrupt_rm(uint32_t x)
93c9512bcaSAntonio Nino Diaz {
94c9512bcaSAntonio Nino Diaz 	if ((x == INTR_SEL1_VALID_RM0) || (x == INTR_SEL1_VALID_RM1))
95c9512bcaSAntonio Nino Diaz 		return 0;
96c9512bcaSAntonio Nino Diaz 
97c9512bcaSAntonio Nino Diaz 	return -EINVAL;
98c9512bcaSAntonio Nino Diaz }
99c9512bcaSAntonio Nino Diaz 
100c9512bcaSAntonio Nino Diaz static inline int32_t validate_ns_interrupt_rm(uint32_t x)
101c9512bcaSAntonio Nino Diaz {
102c9512bcaSAntonio Nino Diaz 	if ((x == INTR_NS_VALID_RM0) || (x == INTR_NS_VALID_RM1))
103c9512bcaSAntonio Nino Diaz 		return 0;
104c9512bcaSAntonio Nino Diaz 
105c9512bcaSAntonio Nino Diaz 	return -EINVAL;
106c9512bcaSAntonio Nino Diaz }
107c9512bcaSAntonio Nino Diaz 
108c9512bcaSAntonio Nino Diaz static inline int32_t validate_el3_interrupt_rm(uint32_t x)
109c9512bcaSAntonio Nino Diaz {
110c9512bcaSAntonio Nino Diaz #if EL3_EXCEPTION_HANDLING
111c9512bcaSAntonio Nino Diaz 	/*
112c9512bcaSAntonio Nino Diaz 	 * With EL3 exception handling, EL3 interrupts are always routed to EL3
113c9512bcaSAntonio Nino Diaz 	 * from both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is
114c9512bcaSAntonio Nino Diaz 	 * the only valid routing model.
115c9512bcaSAntonio Nino Diaz 	 */
116c9512bcaSAntonio Nino Diaz 	if (x == INTR_EL3_VALID_RM1)
117c9512bcaSAntonio Nino Diaz 		return 0;
118c9512bcaSAntonio Nino Diaz #else
119c9512bcaSAntonio Nino Diaz 	if ((x == INTR_EL3_VALID_RM0) || (x == INTR_EL3_VALID_RM1))
120c9512bcaSAntonio Nino Diaz 		return 0;
121c9512bcaSAntonio Nino Diaz #endif
122c9512bcaSAntonio Nino Diaz 
123c9512bcaSAntonio Nino Diaz 	return -EINVAL;
124c9512bcaSAntonio Nino Diaz }
125c9512bcaSAntonio Nino Diaz 
126c9512bcaSAntonio Nino Diaz /*******************************************************************************
127c9512bcaSAntonio Nino Diaz  * Prototype for defining a handler for an interrupt type
128c9512bcaSAntonio Nino Diaz  ******************************************************************************/
129e1333f75SAchin Gupta typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
130e1333f75SAchin Gupta 					     uint32_t flags,
131e1333f75SAchin Gupta 					     void *handle,
132e1333f75SAchin Gupta 					     void *cookie);
133e1333f75SAchin Gupta 
134e1333f75SAchin Gupta /*******************************************************************************
135e1333f75SAchin Gupta  * Function & variable prototypes
136e1333f75SAchin Gupta  ******************************************************************************/
137c6bc0710SDan Handley uint32_t get_scr_el3_from_routing_model(uint32_t security_state);
138c6bc0710SDan Handley int32_t set_routing_model(uint32_t type, uint32_t flags);
139c6bc0710SDan Handley int32_t register_interrupt_type_handler(uint32_t type,
140e1333f75SAchin Gupta 					interrupt_type_handler_t handler,
141e1333f75SAchin Gupta 					uint32_t flags);
1429fb8af33SRoberto Vargas interrupt_type_handler_t get_interrupt_type_handler(uint32_t type);
143f4f1ae77SSoby Mathew int disable_intr_rm_local(uint32_t type, uint32_t security_state);
144f4f1ae77SSoby Mathew int enable_intr_rm_local(uint32_t type, uint32_t security_state);
145e1333f75SAchin Gupta 
146e1333f75SAchin Gupta #endif /*__ASSEMBLY__*/
147c3cf06f1SAntonio Nino Diaz #endif /* INTERRUPT_MGMT_H */
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