1e1333f75SAchin Gupta /* 2e1333f75SAchin Gupta * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3e1333f75SAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5e1333f75SAchin Gupta */ 6e1333f75SAchin Gupta 7e1333f75SAchin Gupta #ifndef __INTERRUPT_MGMT_H__ 8e1333f75SAchin Gupta #define __INTERRUPT_MGMT_H__ 9e1333f75SAchin Gupta 10e1333f75SAchin Gupta #include <arch.h> 11e1333f75SAchin Gupta 12e1333f75SAchin Gupta /******************************************************************************* 13e1333f75SAchin Gupta * Constants for the types of interrupts recognised by the IM framework 14e1333f75SAchin Gupta ******************************************************************************/ 15*030567e6SVarun Wadekar #define INTR_TYPE_S_EL1 U(0) 16*030567e6SVarun Wadekar #define INTR_TYPE_EL3 U(1) 17*030567e6SVarun Wadekar #define INTR_TYPE_NS U(2) 18*030567e6SVarun Wadekar #define MAX_INTR_TYPES U(3) 19e1333f75SAchin Gupta #define INTR_TYPE_INVAL MAX_INTR_TYPES 20e1333f75SAchin Gupta /* 21e1333f75SAchin Gupta * Constant passed to the interrupt handler in the 'id' field when the 22e1333f75SAchin Gupta * framework does not read the gic registers to determine the interrupt id. 23e1333f75SAchin Gupta */ 24*030567e6SVarun Wadekar #define INTR_ID_UNAVAILABLE U(0xFFFFFFFF) 25e1333f75SAchin Gupta 26e1333f75SAchin Gupta 27e1333f75SAchin Gupta /******************************************************************************* 28e1333f75SAchin Gupta * Mask for _both_ the routing model bits in the 'flags' parameter and 29e1333f75SAchin Gupta * constants to define the valid routing models for each supported interrupt 30e1333f75SAchin Gupta * type 31e1333f75SAchin Gupta ******************************************************************************/ 32*030567e6SVarun Wadekar #define INTR_RM_FLAGS_SHIFT U(0x0) 33*030567e6SVarun Wadekar #define INTR_RM_FLAGS_MASK U(0x3) 34e1333f75SAchin Gupta /* Routed to EL3 from NS. Taken to S-EL1 from Secure */ 35*030567e6SVarun Wadekar #define INTR_SEL1_VALID_RM0 U(0x2) 36e1333f75SAchin Gupta /* Routed to EL3 from NS and Secure */ 37*030567e6SVarun Wadekar #define INTR_SEL1_VALID_RM1 U(0x3) 38e1333f75SAchin Gupta /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ 39*030567e6SVarun Wadekar #define INTR_NS_VALID_RM0 U(0x0) 40e1333f75SAchin Gupta /* Routed to EL1/EL2 from NS and to EL3 from Secure */ 41*030567e6SVarun Wadekar #define INTR_NS_VALID_RM1 U(0x1) 424e0e0f44SSoby Mathew /* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */ 43*030567e6SVarun Wadekar #define INTR_EL3_VALID_RM0 U(0x2) 444e0e0f44SSoby Mathew /* Routed to EL3 from NS and Secure */ 45*030567e6SVarun Wadekar #define INTR_EL3_VALID_RM1 U(0x3) 46f4f1ae77SSoby Mathew /* This is the default routing model */ 47*030567e6SVarun Wadekar #define INTR_DEFAULT_RM U(0x0) 48e1333f75SAchin Gupta 49e1333f75SAchin Gupta /******************************************************************************* 50e1333f75SAchin Gupta * Constants for the _individual_ routing model bits in the 'flags' field for 51e1333f75SAchin Gupta * each interrupt type and mask to validate the 'flags' parameter while 52e1333f75SAchin Gupta * registering an interrupt handler 53e1333f75SAchin Gupta ******************************************************************************/ 54*030567e6SVarun Wadekar #define INTR_TYPE_FLAGS_MASK U(0xFFFFFFFC) 55e1333f75SAchin Gupta 56e1333f75SAchin Gupta #define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ 57e1333f75SAchin Gupta #define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ 58*030567e6SVarun Wadekar #define INTR_RM_FROM_FLAG_MASK U(1) 59e1333f75SAchin Gupta #define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ 60e1333f75SAchin Gupta & INTR_RM_FROM_FLAG_MASK) 61*030567e6SVarun Wadekar #define set_interrupt_rm_flag(flag, ss) (flag |= U(1) << ss) 62*030567e6SVarun Wadekar #define clr_interrupt_rm_flag(flag, ss) (flag &= ~(U(1) << ss)) 63e1333f75SAchin Gupta 64e1333f75SAchin Gupta 65e1333f75SAchin Gupta /******************************************************************************* 66e1333f75SAchin Gupta * Macros to validate the routing model bits in the 'flags' for a type 67e1333f75SAchin Gupta * of interrupt. If the model does not match one of the valid masks 68e1333f75SAchin Gupta * -EINVAL is returned. 69e1333f75SAchin Gupta ******************************************************************************/ 704e0e0f44SSoby Mathew #define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \ 714e0e0f44SSoby Mathew ((x) == INTR_SEL1_VALID_RM1 ? 0 :\ 72e1333f75SAchin Gupta -EINVAL)) 73e1333f75SAchin Gupta 744e0e0f44SSoby Mathew #define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \ 754e0e0f44SSoby Mathew ((x) == INTR_NS_VALID_RM1 ? 0 :\ 764e0e0f44SSoby Mathew -EINVAL)) 774e0e0f44SSoby Mathew 784e0e0f44SSoby Mathew #define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \ 794e0e0f44SSoby Mathew ((x) == INTR_EL3_VALID_RM1 ? 0 :\ 80e1333f75SAchin Gupta -EINVAL)) 81e1333f75SAchin Gupta 82e1333f75SAchin Gupta /******************************************************************************* 83e1333f75SAchin Gupta * Macros to set the 'flags' parameter passed to an interrupt type handler. Only 84e1333f75SAchin Gupta * the flag to indicate the security state when the exception was generated is 85e1333f75SAchin Gupta * supported. 86e1333f75SAchin Gupta ******************************************************************************/ 87*030567e6SVarun Wadekar #define INTR_SRC_SS_FLAG_SHIFT U(0) /* BIT[0] */ 88*030567e6SVarun Wadekar #define INTR_SRC_SS_FLAG_MASK U(1) 89e1333f75SAchin Gupta #define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) 90*030567e6SVarun Wadekar #define clr_interrupt_src_ss(flag) (flag &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT)) 91e1333f75SAchin Gupta #define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ 92e1333f75SAchin Gupta INTR_SRC_SS_FLAG_MASK) 93e1333f75SAchin Gupta 94e1333f75SAchin Gupta #ifndef __ASSEMBLY__ 95e1333f75SAchin Gupta 96e1333f75SAchin Gupta /* Prototype for defining a handler for an interrupt type */ 97e1333f75SAchin Gupta typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, 98e1333f75SAchin Gupta uint32_t flags, 99e1333f75SAchin Gupta void *handle, 100e1333f75SAchin Gupta void *cookie); 101e1333f75SAchin Gupta 102e1333f75SAchin Gupta /******************************************************************************* 103e1333f75SAchin Gupta * Function & variable prototypes 104e1333f75SAchin Gupta ******************************************************************************/ 105c6bc0710SDan Handley uint32_t get_scr_el3_from_routing_model(uint32_t security_state); 106c6bc0710SDan Handley int32_t set_routing_model(uint32_t type, uint32_t flags); 107c6bc0710SDan Handley int32_t register_interrupt_type_handler(uint32_t type, 108e1333f75SAchin Gupta interrupt_type_handler_t handler, 109e1333f75SAchin Gupta uint32_t flags); 110c6bc0710SDan Handley interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type); 111f4f1ae77SSoby Mathew int disable_intr_rm_local(uint32_t type, uint32_t security_state); 112f4f1ae77SSoby Mathew int enable_intr_rm_local(uint32_t type, uint32_t security_state); 113e1333f75SAchin Gupta 114e1333f75SAchin Gupta #endif /*__ASSEMBLY__*/ 115e1333f75SAchin Gupta #endif /* __INTERRUPT_MGMT_H__ */ 116