1/* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12 13 /* 14 * Helper macro to initialise EL3 registers we care about. 15 */ 16 .macro el3_arch_init_common 17 /* --------------------------------------------------------------------- 18 * SCTLR_EL3 has already been initialised - read current value before 19 * modifying. 20 * 21 * SCTLR_EL3.I: Enable the instruction cache. 22 * 23 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 24 * exception is generated if a load or store instruction executed at 25 * EL3 uses the SP as the base address and the SP is not aligned to a 26 * 16-byte boundary. 27 * 28 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 29 * load or store one or more registers have an alignment check that the 30 * address being accessed is aligned to the size of the data element(s) 31 * being accessed. 32 * --------------------------------------------------------------------- 33 */ 34 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 35 mrs x0, sctlr_el3 36 orr x0, x0, x1 37 msr sctlr_el3, x0 38 isb 39 40#ifdef IMAGE_BL31 41 /* --------------------------------------------------------------------- 42 * Initialise the per-cpu cache pointer to the CPU. 43 * This is done early to enable crash reporting to have access to crash 44 * stack. Since crash reporting depends on cpu_data to report the 45 * unhandled exception, not doing so can lead to recursive exceptions 46 * due to a NULL TPIDR_EL3. 47 * --------------------------------------------------------------------- 48 */ 49 bl init_cpu_data_ptr 50#endif /* IMAGE_BL31 */ 51 52 /* --------------------------------------------------------------------- 53 * Initialise SCR_EL3, setting all fields rather than relying on hw. 54 * All fields are architecturally UNKNOWN on reset. The following fields 55 * do not change during the TF lifetime. The remaining fields are set to 56 * zero here but are updated ahead of transitioning to a lower EL in the 57 * function cm_init_context_common(). 58 * 59 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 60 * EL2, EL1 and EL0 are not trapped to EL3. 61 * 62 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 63 * EL2, EL1 and EL0 are not trapped to EL3. 64 * 65 * SCR_EL3.SIF: Set to one to disable instruction fetches from 66 * Non-secure memory. 67 * 68 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 69 * both Security states and both Execution states. 70 * 71 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 72 * to EL3 when executing at any EL. 73 * 74 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 75 * disable traps to EL3 when accessing key registers or using pointer 76 * authentication instructions from lower ELs. 77 * --------------------------------------------------------------------- 78 */ 79 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 80 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 81#if CTX_INCLUDE_PAUTH_REGS 82 /* 83 * If the pointer authentication registers are saved during world 84 * switches, enable pointer authentication everywhere, as it is safe to 85 * do so. 86 */ 87 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 88#endif 89 msr scr_el3, x0 90 91 /* --------------------------------------------------------------------- 92 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 93 * Some fields are architecturally UNKNOWN on reset. 94 * 95 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 96 * Debug exceptions, other than Breakpoint Instruction exceptions, are 97 * disabled from all ELs in Secure state. 98 * 99 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 100 * privileged debug from S-EL1. 101 * 102 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 103 * access to the powerdown debug registers do not trap to EL3. 104 * 105 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 106 * debug registers, other than those registers that are controlled by 107 * MDCR_EL3.TDOSA. 108 * 109 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 110 * accesses to all Performance Monitors registers do not trap to EL3. 111 * 112 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 113 * prohibited in Secure state. This bit is RES0 in versions of the 114 * architecture earlier than ARMv8.5, setting it to 1 doesn't have any 115 * effect on them. 116 * --------------------------------------------------------------------- 117 */ 118 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 119 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \ 120 ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT)) 121 122 msr mdcr_el3, x0 123 124 /* --------------------------------------------------------------------- 125 * Initialise PMCR_EL0 setting all fields rather than relying 126 * on hw. Some fields are architecturally UNKNOWN on reset. 127 * 128 * PMCR_EL0.LP: Set to one so that event counter overflow, that 129 * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment 130 * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU 131 * is implemented. This bit is RES0 in versions of the architecture 132 * earlier than ARMv8.5, setting it to 1 doesn't have any effect 133 * on them. 134 * 135 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 136 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 137 * that changes PMCCNTR_EL0[63] from 1 to 0. 138 * 139 * PMCR_EL0.DP: Set to one so that the cycle counter, 140 * PMCCNTR_EL0 does not count when event counting is prohibited. 141 * 142 * PMCR_EL0.X: Set to zero to disable export of events. 143 * 144 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 145 * counts on every clock cycle. 146 * --------------------------------------------------------------------- 147 */ 148 mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ 149 PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ 150 ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) 151 152 msr pmcr_el0, x0 153 154 /* --------------------------------------------------------------------- 155 * Enable External Aborts and SError Interrupts now that the exception 156 * vectors have been setup. 157 * --------------------------------------------------------------------- 158 */ 159 msr daifclr, #DAIF_ABT_BIT 160 161 /* --------------------------------------------------------------------- 162 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 163 * All fields are architecturally UNKNOWN on reset. 164 * 165 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 166 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 167 * 168 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 169 * trace registers do not trap to EL3. 170 * 171 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 172 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 173 * do not trap to EL3. 174 */ 175 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 176 msr cptr_el3, x0 177 178 /* 179 * If Data Independent Timing (DIT) functionality is implemented, 180 * always enable DIT in EL3 181 */ 182 mrs x0, id_aa64pfr0_el1 183 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 184 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 185 bne 1f 186 mov x0, #DIT_BIT 187 msr DIT, x0 1881: 189 .endm 190 191/* ----------------------------------------------------------------------------- 192 * This is the super set of actions that need to be performed during a cold boot 193 * or a warm boot in EL3. This code is shared by BL1 and BL31. 194 * 195 * This macro will always perform reset handling, architectural initialisations 196 * and stack setup. The rest of the actions are optional because they might not 197 * be needed, depending on the context in which this macro is called. This is 198 * why this macro is parameterised ; each parameter allows to enable/disable 199 * some actions. 200 * 201 * _init_sctlr: 202 * Whether the macro needs to initialise SCTLR_EL3, including configuring 203 * the endianness of data accesses. 204 * 205 * _warm_boot_mailbox: 206 * Whether the macro needs to detect the type of boot (cold/warm). The 207 * detection is based on the platform entrypoint address : if it is zero 208 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 209 * this macro jumps on the platform entrypoint address. 210 * 211 * _secondary_cold_boot: 212 * Whether the macro needs to identify the CPU that is calling it: primary 213 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 214 * the platform initialisations, while the secondaries will be put in a 215 * platform-specific state in the meantime. 216 * 217 * If the caller knows this macro will only be called by the primary CPU 218 * then this parameter can be defined to 0 to skip this step. 219 * 220 * _init_memory: 221 * Whether the macro needs to initialise the memory. 222 * 223 * _init_c_runtime: 224 * Whether the macro needs to initialise the C runtime environment. 225 * 226 * _exception_vectors: 227 * Address of the exception vectors to program in the VBAR_EL3 register. 228 * ----------------------------------------------------------------------------- 229 */ 230 .macro el3_entrypoint_common \ 231 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 232 _init_memory, _init_c_runtime, _exception_vectors 233 234 .if \_init_sctlr 235 /* ------------------------------------------------------------- 236 * This is the initialisation of SCTLR_EL3 and so must ensure 237 * that all fields are explicitly set rather than relying on hw. 238 * Some fields reset to an IMPLEMENTATION DEFINED value and 239 * others are architecturally UNKNOWN on reset. 240 * 241 * SCTLR.EE: Set the CPU endianness before doing anything that 242 * might involve memory reads or writes. Set to zero to select 243 * Little Endian. 244 * 245 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 246 * force all memory regions that are writeable to be treated as 247 * XN (Execute-never). Set to zero so that this control has no 248 * effect on memory access permissions. 249 * 250 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 251 * 252 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 253 * 254 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 255 * safe behaviour upon exception entry to EL3. 256 * ------------------------------------------------------------- 257 */ 258 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 259 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 260 msr sctlr_el3, x0 261 isb 262 .endif /* _init_sctlr */ 263 264 .if \_warm_boot_mailbox 265 /* ------------------------------------------------------------- 266 * This code will be executed for both warm and cold resets. 267 * Now is the time to distinguish between the two. 268 * Query the platform entrypoint address and if it is not zero 269 * then it means it is a warm boot so jump to this address. 270 * ------------------------------------------------------------- 271 */ 272 bl plat_get_my_entrypoint 273 cbz x0, do_cold_boot 274 br x0 275 276 do_cold_boot: 277 .endif /* _warm_boot_mailbox */ 278 279 /* --------------------------------------------------------------------- 280 * Set the exception vectors. 281 * --------------------------------------------------------------------- 282 */ 283 adr x0, \_exception_vectors 284 msr vbar_el3, x0 285 isb 286 287 /* --------------------------------------------------------------------- 288 * It is a cold boot. 289 * Perform any processor specific actions upon reset e.g. cache, TLB 290 * invalidations etc. 291 * --------------------------------------------------------------------- 292 */ 293 bl reset_handler 294 295 el3_arch_init_common 296 297 .if \_secondary_cold_boot 298 /* ------------------------------------------------------------- 299 * Check if this is a primary or secondary CPU cold boot. 300 * The primary CPU will set up the platform while the 301 * secondaries are placed in a platform-specific state until the 302 * primary CPU performs the necessary actions to bring them out 303 * of that state and allows entry into the OS. 304 * ------------------------------------------------------------- 305 */ 306 bl plat_is_my_cpu_primary 307 cbnz w0, do_primary_cold_boot 308 309 /* This is a cold boot on a secondary CPU */ 310 bl plat_secondary_cold_boot_setup 311 /* plat_secondary_cold_boot_setup() is not supposed to return */ 312 bl el3_panic 313 314 do_primary_cold_boot: 315 .endif /* _secondary_cold_boot */ 316 317 /* --------------------------------------------------------------------- 318 * Initialize memory now. Secondary CPU initialization won't get to this 319 * point. 320 * --------------------------------------------------------------------- 321 */ 322 323 .if \_init_memory 324 bl platform_mem_init 325 .endif /* _init_memory */ 326 327 /* --------------------------------------------------------------------- 328 * Init C runtime environment: 329 * - Zero-initialise the NOBITS sections. There are 2 of them: 330 * - the .bss section; 331 * - the coherent memory section (if any). 332 * - Relocate the data section from ROM to RAM, if required. 333 * --------------------------------------------------------------------- 334 */ 335 .if \_init_c_runtime 336#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3) 337 /* ------------------------------------------------------------- 338 * Invalidate the RW memory used by the BL31 image. This 339 * includes the data and NOBITS sections. This is done to 340 * safeguard against possible corruption of this memory by 341 * dirty cache lines in a system cache as a result of use by 342 * an earlier boot loader stage. 343 * ------------------------------------------------------------- 344 */ 345 adrp x0, __RW_START__ 346 add x0, x0, :lo12:__RW_START__ 347 adrp x1, __RW_END__ 348 add x1, x1, :lo12:__RW_END__ 349 sub x1, x1, x0 350 bl inv_dcache_range 351#endif 352 adrp x0, __BSS_START__ 353 add x0, x0, :lo12:__BSS_START__ 354 355 adrp x1, __BSS_END__ 356 add x1, x1, :lo12:__BSS_END__ 357 sub x1, x1, x0 358 bl zeromem 359 360#if USE_COHERENT_MEM 361 adrp x0, __COHERENT_RAM_START__ 362 add x0, x0, :lo12:__COHERENT_RAM_START__ 363 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 364 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 365 sub x1, x1, x0 366 bl zeromem 367#endif 368 369#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM) 370 adrp x0, __DATA_RAM_START__ 371 add x0, x0, :lo12:__DATA_RAM_START__ 372 adrp x1, __DATA_ROM_START__ 373 add x1, x1, :lo12:__DATA_ROM_START__ 374 adrp x2, __DATA_RAM_END__ 375 add x2, x2, :lo12:__DATA_RAM_END__ 376 sub x2, x2, x0 377 bl memcpy16 378#endif 379 .endif /* _init_c_runtime */ 380 381 /* --------------------------------------------------------------------- 382 * Use SP_EL0 for the C runtime stack. 383 * --------------------------------------------------------------------- 384 */ 385 msr spsel, #0 386 387 /* --------------------------------------------------------------------- 388 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 389 * the MMU is enabled. There is no risk of reading stale stack memory 390 * after enabling the MMU as only the primary CPU is running at the 391 * moment. 392 * --------------------------------------------------------------------- 393 */ 394 bl plat_set_my_stack 395 396#if STACK_PROTECTOR_ENABLED 397 .if \_init_c_runtime 398 bl update_stack_protector_canary 399 .endif /* _init_c_runtime */ 400#endif 401 .endm 402 403#endif /* EL3_COMMON_MACROS_S */ 404