1/* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/el3_runtime/cpu_data.h> 15#include <lib/per_cpu/per_cpu_macros.S> 16 17 /* 18 * Helper macro to initialise EL3 registers we care about. 19 */ 20 .macro el3_arch_init_common 21 /* --------------------------------------------------------------------- 22 * SCTLR_EL3 has already been initialised - read current value before 23 * modifying. 24 * 25 * SCTLR_EL3.I: Enable the instruction cache. 26 * 27 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 28 * exception is generated if a load or store instruction executed at 29 * EL3 uses the SP as the base address and the SP is not aligned to a 30 * 16-byte boundary. 31 * 32 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 33 * load or store one or more registers have an alignment check that the 34 * address being accessed is aligned to the size of the data element(s) 35 * being accessed. 36 * 37 * SCTLR_EL3.BT: PAuth instructions are compatible with bti jc 38 * --------------------------------------------------------------------- 39 */ 40 mov_imm x1, (SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 41 mrs x0, sctlr_el3 42#if ENABLE_BTI 43 bic x0, x0, #SCTLR_BT_BIT 44#endif 45 orr x0, x0, x1 46 msr sctlr_el3, x0 47 isb 48 49#if ENABLE_FEAT_SCTLR2 50#if ENABLE_FEAT_SCTLR2 > 1 51 is_feat_sctlr2_present_asm x1 52 beq feat_sctlr2_not_supported\@ 53#endif 54 mov x1, #SCTLR2_RESET_VAL 55 msr SCTLR2_EL3, x1 56feat_sctlr2_not_supported\@: 57#endif 58 59#ifdef IMAGE_BL31 60 /* --------------------------------------------------------------------- 61 * Initialise the per-cpu framework to utilize tpidr_el3. 62 * 63 * This is done early to enable crash reporting to have access to crash 64 * stack. Since crash reporting depends on cpu_data to report the 65 * unhandled exception, not doing so can lead to recursive exceptions 66 * due to a NULL TPIDR_EL3. 67 * --------------------------------------------------------------------- 68 */ 69 per_cpu_init 70#endif /* IMAGE_BL31 */ 71 72 /* --------------------------------------------------------------------- 73 * Initialise SCR_EL3, setting all fields rather than relying on hw. 74 * All fields are architecturally UNKNOWN on reset. The following fields 75 * do not change during the TF lifetime. The remaining fields are set to 76 * zero here but are updated ahead of transitioning to a lower EL in the 77 * function cm_init_context_common(). 78 * 79 * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled. 80 * 81 * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate 82 * against ERRATA_V2_3099206. 83 * --------------------------------------------------------------------- 84 */ 85 mov_imm x0, SCR_RESET_VAL 86#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 87 mrs x1, id_aa64pfr0_el1 88 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT) 89 cbz x1, 1f 90 orr x0, x0, #SCR_EEL2_BIT 91#endif 921: 93 msr scr_el3, x0 94 95 /* --------------------------------------------------------------------- 96 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 97 * Some fields are architecturally UNKNOWN on reset. 98 */ 99 mov_imm x0, MDCR_EL3_RESET_VAL 100 msr mdcr_el3, x0 101 102 /* --------------------------------------------------------------------- 103 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 104 * All fields are architecturally UNKNOWN on reset. 105 * --------------------------------------------------------------------- 106 */ 107 mov_imm x0, CPTR_EL3_RESET_VAL 108 msr cptr_el3, x0 109 110 .endm 111 112/* ----------------------------------------------------------------------------- 113 * This is the super set of actions that need to be performed during a cold boot 114 * or a warm boot in EL3. This code is shared by BL1 and BL31. 115 * 116 * This macro will always perform reset handling, architectural initialisations 117 * and stack setup. The rest of the actions are optional because they might not 118 * be needed, depending on the context in which this macro is called. This is 119 * why this macro is parameterised ; each parameter allows to enable/disable 120 * some actions. 121 * 122 * _init_sctlr: 123 * Whether the macro needs to initialise SCTLR_EL3, including configuring 124 * the endianness of data accesses. 125 * 126 * _warm_boot_mailbox: 127 * Whether the macro needs to detect the type of boot (cold/warm). The 128 * detection is based on the platform entrypoint address : if it is zero 129 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 130 * this macro jumps on the platform entrypoint address. 131 * 132 * _secondary_cold_boot: 133 * Whether the macro needs to identify the CPU that is calling it: primary 134 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 135 * the platform initialisations, while the secondaries will be put in a 136 * platform-specific state in the meantime. 137 * 138 * If the caller knows this macro will only be called by the primary CPU 139 * then this parameter can be defined to 0 to skip this step. 140 * 141 * _init_memory: 142 * Whether the macro needs to initialise the memory. 143 * 144 * _init_c_runtime: 145 * Whether the macro needs to initialise the C runtime environment. 146 * 147 * _exception_vectors: 148 * Address of the exception vectors to program in the VBAR_EL3 register. 149 * 150 * _pie_fixup_size: 151 * Size of memory region to fixup Global Descriptor Table (GDT). 152 * 153 * A non-zero value is expected when firmware needs GDT to be fixed-up. 154 * 155 * ----------------------------------------------------------------------------- 156 */ 157 .macro el3_entrypoint_common \ 158 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 159 _init_memory, _init_c_runtime, _exception_vectors, \ 160 _pie_fixup_size 161 162 .if \_init_sctlr 163 /* ------------------------------------------------------------- 164 * This is the initialisation of SCTLR_EL3 and so must ensure 165 * that all fields are explicitly set rather than relying on hw. 166 * Some fields reset to an IMPLEMENTATION DEFINED value and 167 * others are architecturally UNKNOWN on reset. 168 * 169 * SCTLR.EE: Set the CPU endianness before doing anything that 170 * might involve memory reads or writes. Set to zero to select 171 * Little Endian. 172 * 173 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 174 * force all memory regions that are writeable to be treated as 175 * XN (Execute-never). Set to zero so that this control has no 176 * effect on memory access permissions. 177 * 178 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 179 * 180 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 181 * 182 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 183 * safe behaviour upon exception entry to EL3. 184 * ------------------------------------------------------------- 185 */ 186 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 187 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 188#if ENABLE_FEAT_RAS 189 /* If FEAT_RAS is present assume FEAT_IESB is also present */ 190 orr x0, x0, #SCTLR_IESB_BIT 191#endif 192 msr sctlr_el3, x0 193 isb 194 .endif /* _init_sctlr */ 195 196 .if \_warm_boot_mailbox 197 /* ------------------------------------------------------------- 198 * This code will be executed for both warm and cold resets. 199 * Now is the time to distinguish between the two. 200 * Query the platform entrypoint address and if it is not zero 201 * then it means it is a warm boot so jump to this address. 202 * ------------------------------------------------------------- 203 */ 204 bl plat_get_my_entrypoint 205 cbz x0, do_cold_boot 206 br x0 207 208 do_cold_boot: 209 .endif /* _warm_boot_mailbox */ 210 211 .if \_pie_fixup_size 212#if ENABLE_PIE 213 /* 214 * ------------------------------------------------------------ 215 * If PIE is enabled fixup the Global descriptor Table only 216 * once during primary core cold boot path. 217 * 218 * Compile time base address, required for fixup, is calculated 219 * using "pie_fixup" label present within first page. 220 * ------------------------------------------------------------ 221 */ 222 pie_fixup: 223 ldr x0, =pie_fixup 224 and x0, x0, #~(PAGE_SIZE_MASK) 225 mov_imm x1, \_pie_fixup_size 226 add x1, x1, x0 227 bl fixup_gdt_reloc 228#endif /* ENABLE_PIE */ 229 .endif /* _pie_fixup_size */ 230 231 /* --------------------------------------------------------------------- 232 * Set the exception vectors. 233 * --------------------------------------------------------------------- 234 */ 235 adr x0, \_exception_vectors 236 msr vbar_el3, x0 237 isb 238 239 call_reset_handler 240 241 el3_arch_init_common 242 243 /* --------------------------------------------------------------------- 244 * Set the el3 execution context(i.e. root_context). 245 * --------------------------------------------------------------------- 246 */ 247 setup_el3_execution_context 248 249 .if \_secondary_cold_boot 250 /* ------------------------------------------------------------- 251 * Check if this is a primary or secondary CPU cold boot. 252 * The primary CPU will set up the platform while the 253 * secondaries are placed in a platform-specific state until the 254 * primary CPU performs the necessary actions to bring them out 255 * of that state and allows entry into the OS. 256 * ------------------------------------------------------------- 257 */ 258 bl plat_is_my_cpu_primary 259 cbnz w0, do_primary_cold_boot 260 261 /* This is a cold boot on a secondary CPU */ 262 bl plat_secondary_cold_boot_setup 263 /* plat_secondary_cold_boot_setup() is not supposed to return */ 264 bl el3_panic 265 266 do_primary_cold_boot: 267 .endif /* _secondary_cold_boot */ 268 269 /* --------------------------------------------------------------------- 270 * Initialize memory now. Secondary CPU initialization won't get to this 271 * point. 272 * --------------------------------------------------------------------- 273 */ 274 275 .if \_init_memory 276 bl platform_mem_init 277 .endif /* _init_memory */ 278 279 /* --------------------------------------------------------------------- 280 * Init C runtime environment: 281 * - Zero-initialise the NOBITS sections. There are 2 of them: 282 * - the .bss section; 283 * - the coherent memory section (if any). 284 * - Relocate the data section from ROM to RAM, if required. 285 * --------------------------------------------------------------------- 286 */ 287 .if \_init_c_runtime 288#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 289 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 290 /* ------------------------------------------------------------- 291 * Invalidate the RW memory used by the BL31 image. This 292 * includes the data and NOBITS sections. This is done to 293 * safeguard against possible corruption of this memory by 294 * dirty cache lines in a system cache as a result of use by 295 * an earlier boot loader stage. If PIE is enabled however, 296 * RO sections including the GOT may be modified during 297 * pie fixup. Therefore, to be on the safe side, invalidate 298 * the entire image region if PIE is enabled. 299 * ------------------------------------------------------------- 300 */ 301#if ENABLE_PIE 302#if SEPARATE_CODE_AND_RODATA 303 adrp x0, __TEXT_START__ 304 add x0, x0, :lo12:__TEXT_START__ 305#else 306 adrp x0, __RO_START__ 307 add x0, x0, :lo12:__RO_START__ 308#endif /* SEPARATE_CODE_AND_RODATA */ 309#else 310 adrp x0, __RW_START__ 311 add x0, x0, :lo12:__RW_START__ 312#endif /* ENABLE_PIE */ 313 adrp x1, __RW_END__ 314 add x1, x1, :lo12:__RW_END__ 315 sub x1, x1, x0 316 bl inv_dcache_range 317#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 318 adrp x0, __NOBITS_START__ 319 add x0, x0, :lo12:__NOBITS_START__ 320 adrp x1, __NOBITS_END__ 321 add x1, x1, :lo12:__NOBITS_END__ 322 sub x1, x1, x0 323 bl inv_dcache_range 324#endif 325#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 326 adrp x0, __BL2_NOLOAD_START__ 327 add x0, x0, :lo12:__BL2_NOLOAD_START__ 328 adrp x1, __BL2_NOLOAD_END__ 329 add x1, x1, :lo12:__BL2_NOLOAD_END__ 330 sub x1, x1, x0 331 bl inv_dcache_range 332#endif 333#endif 334#if defined(IMAGE_BL31) 335 adrp x0, __PER_CPU_START__ 336 add x0, x0, :lo12:__PER_CPU_START__ 337 adrp x1, __PER_CPU_END__ 338 add x1, x1, :lo12:__PER_CPU_END__ 339 sub x1, x1, x0 340#if (PLATFORM_NODE_COUNT > 1) 341 mov x9, x1 342#endif /* (PLATFORM_NODE_COUNT > 1) */ 343 bl zeromem 344#if (PLATFORM_NODE_COUNT > 1) 345 /* 346 * Zero-initialize per-cpu sections defined by the platform. 347 * Care must be taken to preserve and retain the clobbered 348 * registers. A standard around the container for per-cpu nodes 349 * is not yet defined. 350 */ 351 mov x10, #1 352 mov x11, #PLATFORM_NODE_COUNT 353 354 1: 355 cmp x10, x11 356 b.hs 2f 357 358 mov x0, x10 359 bl plat_per_cpu_node_base 360 cmn x0, #1 361 b.eq 3f 362 363 /* x1 contains size param */ 364 mov x1, x9 365 bl zeromem 366 367 3: 368 add x10, x10, #1 369 b 1b 370 371 2: 372#endif /* (PLATFORM_NODE_COUNT > 1) */ 373#endif /* defined(IMAGE_BL31) */ 374 375 adrp x0, __BSS_START__ 376 add x0, x0, :lo12:__BSS_START__ 377 378 adrp x1, __BSS_END__ 379 add x1, x1, :lo12:__BSS_END__ 380 sub x1, x1, x0 381 bl zeromem 382 383#if USE_COHERENT_MEM 384 adrp x0, __COHERENT_RAM_START__ 385 add x0, x0, :lo12:__COHERENT_RAM_START__ 386 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 387 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 388 sub x1, x1, x0 389 bl zeromem 390#endif 391 392#if defined(IMAGE_BL1) || \ 393 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) || \ 394 (defined(IMAGE_BL31) && SEPARATE_RWDATA_REGION) 395 396 adrp x0, __DATA_RAM_START__ 397 add x0, x0, :lo12:__DATA_RAM_START__ 398 adrp x1, __DATA_ROM_START__ 399 add x1, x1, :lo12:__DATA_ROM_START__ 400 adrp x2, __DATA_RAM_END__ 401 add x2, x2, :lo12:__DATA_RAM_END__ 402 sub x2, x2, x0 403 bl memcpy16 404#endif 405 .endif /* _init_c_runtime */ 406 407 /* --------------------------------------------------------------------- 408 * Use SP_EL0 for the C runtime stack. 409 * --------------------------------------------------------------------- 410 */ 411 msr spsel, #0 412 413 /* --------------------------------------------------------------------- 414 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 415 * the MMU is enabled. There is no risk of reading stale stack memory 416 * after enabling the MMU as only the primary CPU is running at the 417 * moment. 418 * --------------------------------------------------------------------- 419 */ 420 bl plat_set_my_stack 421 422#if STACK_PROTECTOR_ENABLED 423 .if \_init_c_runtime 424 bl update_stack_protector_canary 425 .endif /* _init_c_runtime */ 426#endif 427 .endm 428 429 .macro apply_at_speculative_wa 430#if ERRATA_SPECULATIVE_AT 431 /* 432 * This function expects x30 has been saved. 433 * Also, save x29 which will be used in the called function. 434 */ 435 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 436 bl save_and_update_ptw_el1_sys_regs 437 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 438#endif 439 .endm 440 441 .macro restore_ptw_el1_sys_regs 442#if ERRATA_SPECULATIVE_AT 443 /* ----------------------------------------------------------- 444 * In case of ERRATA_SPECULATIVE_AT, must follow below order 445 * to ensure that page table walk is not enabled until 446 * restoration of all EL1 system registers. TCR_EL1 register 447 * should be updated at the end which restores previous page 448 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 449 * ensures that CPU does below steps in order. 450 * 451 * 1. Ensure all other system registers are written before 452 * updating SCTLR_EL1 using ISB. 453 * 2. Restore SCTLR_EL1 register. 454 * 3. Ensure SCTLR_EL1 written successfully using ISB. 455 * 4. Restore TCR_EL1 register. 456 * ----------------------------------------------------------- 457 */ 458 isb 459 ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1] 460 msr sctlr_el1, x28 461 isb 462 msr tcr_el1, x29 463#endif 464 .endm 465 466/* ----------------------------------------------------------------- 467 * The below macro reads SCR_EL3 from the context structure to 468 * determine the security state of the context upon ERET. 469 * ------------------------------------------------------------------ 470 */ 471 .macro get_security_state _ret:req, _scr_reg:req 472 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 473 cmp \_ret, #1 474 beq realm_state 475 bfi \_ret, \_scr_reg, #0, #1 476 b end 477 realm_state: 478 mov \_ret, #2 479 end: 480 .endm 481 482/*----------------------------------------------------------------------------- 483 * Helper macro to configure EL3 registers we care about, while executing 484 * at EL3/Root world. Root world has its own execution environment and 485 * needs to have its settings configured to be independent of other worlds. 486 * ----------------------------------------------------------------------------- 487 */ 488 .macro setup_el3_execution_context 489 490 /* --------------------------------------------------------------------- 491 * The following registers need to be part of separate root context 492 * as their values are of importance during EL3 execution. 493 * Hence these registers are overwritten to their intital values, 494 * irrespective of whichever world they return from to ensure EL3 has a 495 * consistent execution context throughout the lifetime of TF-A. 496 * 497 * DAIF.A: Enable External Aborts and SError Interrupts at EL3. 498 * 499 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 500 * Debug exceptions, other than Breakpoint Instruction exceptions, are 501 * disabled from all ELs in Secure state. 502 * 503 * SCR_EL3.EA: Set to one to enable SError interrupts at EL3. 504 * 505 * SCR_EL3.SIF: Set to one to disable instruction fetches from 506 * Non-secure memory. 507 * 508 * PMCR_EL0.DP: Set to one so that the cycle counter, 509 * PMCCNTR_EL0 does not count when event counting is prohibited. 510 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 511 * available. 512 * 513 * CPTR_EL3.EZ: Set to one so that accesses to ZCR_EL3 do not trap 514 * CPTR_EL3.ESM: Set to one so that SME related registers don't trap 515 * 516 * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT) 517 * functionality, if implemented in EL3. 518 * --------------------------------------------------------------------- 519 */ 520 msr daifclr, #DAIF_ABT_BIT 521 522 mrs x15, mdcr_el3 523 orr x15, x15, #MDCR_SDD_BIT 524 msr mdcr_el3, x15 525 526 mrs x15, scr_el3 527 orr x15, x15, #SCR_EA_BIT 528 orr x15, x15, #SCR_SIF_BIT 529 bic x15, x15, #SCR_TRNDR_BIT 530 msr scr_el3, x15 531 532 mrs x15, pmcr_el0 533 orr x15, x15, #PMCR_EL0_DP_BIT 534 msr pmcr_el0, x15 535 536 mrs x15, cptr_el3 537 orr x15, x15, #CPTR_EZ_BIT 538 orr x15, x15, #ESM_BIT 539 msr cptr_el3, x15 540 541#if ENABLE_FEAT_DIT 542#if ENABLE_FEAT_DIT > 1 543 mrs x15, id_aa64pfr0_el1 544 ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 545 cbz x15, 1f 546#endif 547 mov x15, #DIT_BIT 548 msr DIT, x15 549 1: 550#endif 551 552 isb 553 .endm 554 555#endif /* EL3_COMMON_MACROS_S */ 556