1/* 2 * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/el3_runtime/cpu_data.h> 15#include <lib/per_cpu/per_cpu_macros.S> 16 17 /* 18 * Helper macro to initialise EL3 registers we care about. 19 */ 20 .macro el3_arch_init_common 21 /* --------------------------------------------------------------------- 22 * SCTLR_EL3 has already been initialised - read current value before 23 * modifying. 24 * 25 * SCTLR_EL3.I: Enable the instruction cache. 26 * 27 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 28 * exception is generated if a load or store instruction executed at 29 * EL3 uses the SP as the base address and the SP is not aligned to a 30 * 16-byte boundary. 31 * 32 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 33 * load or store one or more registers have an alignment check that the 34 * address being accessed is aligned to the size of the data element(s) 35 * being accessed. 36 * 37 * SCTLR_EL3.BT: PAuth instructions are compatible with bti jc 38 * --------------------------------------------------------------------- 39 */ 40 mov_imm x1, (SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 41 mrs x0, sctlr_el3 42#if ENABLE_BTI 43 bic x0, x0, #SCTLR_BT_BIT 44#endif 45 orr x0, x0, x1 46 msr sctlr_el3, x0 47 isb 48 49#if ENABLE_FEAT_SCTLR2 50#if ENABLE_FEAT_SCTLR2 > 1 51 is_feat_sctlr2_present_asm x1 52 beq feat_sctlr2_not_supported\@ 53#endif 54 mov x1, #SCTLR2_RESET_VAL 55 msr SCTLR2_EL3, x1 56feat_sctlr2_not_supported\@: 57#endif 58 59#ifdef IMAGE_BL31 60 /* --------------------------------------------------------------------- 61 * Initialise the per-cpu cache pointer to the CPU. 62 * --------------------------------------------------------------------- 63 */ 64 per_cpu_init 65#endif /* IMAGE_BL31 */ 66 67 /* --------------------------------------------------------------------- 68 * Initialise SCR_EL3, setting all fields rather than relying on hw. 69 * All fields are architecturally UNKNOWN on reset. The following fields 70 * do not change during the TF lifetime. The remaining fields are set to 71 * zero here but are updated ahead of transitioning to a lower EL in the 72 * function cm_init_context_common(). 73 * 74 * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled. 75 * 76 * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate 77 * against ERRATA_V2_3099206. 78 * --------------------------------------------------------------------- 79 */ 80 mov_imm x0, SCR_RESET_VAL 81#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 82 mrs x1, id_aa64pfr0_el1 83 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT) 84 cbz x1, 1f 85 orr x0, x0, #SCR_EEL2_BIT 86#endif 871: 88 msr scr_el3, x0 89 90 /* --------------------------------------------------------------------- 91 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 92 * Some fields are architecturally UNKNOWN on reset. 93 */ 94 mov_imm x0, MDCR_EL3_RESET_VAL 95 msr mdcr_el3, x0 96 97 /* --------------------------------------------------------------------- 98 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 99 * All fields are architecturally UNKNOWN on reset. 100 * --------------------------------------------------------------------- 101 */ 102 mov_imm x0, CPTR_EL3_RESET_VAL 103 msr cptr_el3, x0 104 105#if ENABLE_FEAT_MORELLO 106#if ENABLE_FEAT_MORELLO == 2 107 is_feat_morello_present_asm x10 108 beq 2f 109#endif /* ENABLE_FEAT_MORELLO == 2 */ 110 /* 111 * SETTAG: disable privileged tag-setting operations 112 */ 113 mov x0, CSCR_EL3_SETTAG 114 msr cscr_el3, x0 115 116 /* 117 * Disable PCC/DCC base offset 118 */ 119 msr cctlr_el3, xzr 1202: 121#endif /* ENABLE_FEAT_MORELLO */ 122 .endm 123 124/* ----------------------------------------------------------------------------- 125 * This is the super set of actions that need to be performed during a cold boot 126 * or a warm boot in EL3. This code is shared by BL1 and BL31. 127 * 128 * This macro will always perform reset handling, architectural initialisations 129 * and stack setup. The rest of the actions are optional because they might not 130 * be needed, depending on the context in which this macro is called. This is 131 * why this macro is parameterised ; each parameter allows to enable/disable 132 * some actions. 133 * 134 * _init_sctlr: 135 * Whether the macro needs to initialise SCTLR_EL3, including configuring 136 * the endianness of data accesses. 137 * 138 * _warm_boot_mailbox: 139 * Whether the macro needs to detect the type of boot (cold/warm). The 140 * detection is based on the platform entrypoint address : if it is zero 141 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 142 * this macro jumps on the platform entrypoint address. 143 * 144 * _secondary_cold_boot: 145 * Whether the macro needs to identify the CPU that is calling it: primary 146 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 147 * the platform initialisations, while the secondaries will be put in a 148 * platform-specific state in the meantime. 149 * 150 * If the caller knows this macro will only be called by the primary CPU 151 * then this parameter can be defined to 0 to skip this step. 152 * 153 * _init_memory: 154 * Whether the macro needs to initialise the memory. 155 * 156 * _init_c_runtime: 157 * Whether the macro needs to initialise the C runtime environment. 158 * 159 * _exception_vectors: 160 * Address of the exception vectors to program in the VBAR_EL3 register. 161 * 162 * _pie_fixup_size: 163 * Size of memory region to fixup Global Descriptor Table (GDT). 164 * 165 * A non-zero value is expected when firmware needs GDT to be fixed-up. 166 * 167 * ----------------------------------------------------------------------------- 168 */ 169 .macro el3_entrypoint_common \ 170 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 171 _init_memory, _init_c_runtime, _exception_vectors, \ 172 _pie_fixup_size 173 174 .if \_init_sctlr 175 /* ------------------------------------------------------------- 176 * This is the initialisation of SCTLR_EL3 and so must ensure 177 * that all fields are explicitly set rather than relying on hw. 178 * Some fields reset to an IMPLEMENTATION DEFINED value and 179 * others are architecturally UNKNOWN on reset. 180 * 181 * SCTLR.EE: Set the CPU endianness before doing anything that 182 * might involve memory reads or writes. Set to zero to select 183 * Little Endian. 184 * 185 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 186 * force all memory regions that are writeable to be treated as 187 * XN (Execute-never). Set to zero so that this control has no 188 * effect on memory access permissions. 189 * 190 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 191 * 192 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 193 * 194 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 195 * safe behaviour upon exception entry to EL3. 196 * ------------------------------------------------------------- 197 */ 198 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 199 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 200#if ENABLE_FEAT_RAS 201 /* If FEAT_RAS is present assume FEAT_IESB is also present */ 202 orr x0, x0, #SCTLR_IESB_BIT 203#endif 204 msr sctlr_el3, x0 205 isb 206 .endif /* _init_sctlr */ 207 208 .if \_warm_boot_mailbox 209 /* ------------------------------------------------------------- 210 * This code will be executed for both warm and cold resets. 211 * Now is the time to distinguish between the two. 212 * Query the platform entrypoint address and if it is not zero 213 * then it means it is a warm boot so jump to this address. 214 * ------------------------------------------------------------- 215 */ 216 bl plat_get_my_entrypoint 217 cbz x0, do_cold_boot 218 br x0 219 220 do_cold_boot: 221 .endif /* _warm_boot_mailbox */ 222 223 .if \_pie_fixup_size 224#if ENABLE_PIE 225 /* 226 * ------------------------------------------------------------ 227 * If PIE is enabled fixup the Global descriptor Table only 228 * once during primary core cold boot path. 229 * 230 * Compile time base address, required for fixup, is calculated 231 * using "pie_fixup" label present within first page. 232 * ------------------------------------------------------------ 233 */ 234 pie_fixup: 235 ldr x0, =pie_fixup 236 and x0, x0, #~(PAGE_SIZE_MASK) 237 mov_imm x1, \_pie_fixup_size 238 add x1, x1, x0 239 bl fixup_gdt_reloc 240#endif /* ENABLE_PIE */ 241 .endif /* _pie_fixup_size */ 242 243 /* --------------------------------------------------------------------------- 244 * Set the exception vectors. 245 * cptr_el3 write needs to be done before the first capability register access 246 * --------------------------------------------------------------------------- 247 */ 248#if ENABLE_FEAT_MORELLO 249 mrs x0, cptr_el3 250 orr x0, x0, #EC_BIT 251 msr cptr_el3, x0 252#endif /* ENABLE_FEAT_MORELLO */ 253 adr x0, \_exception_vectors 254 msr_wide_reg vbar_el3, 0 255 isb 256 257 call_reset_handler 258 259 el3_arch_init_common 260 261 /* --------------------------------------------------------------------- 262 * Set the el3 execution context(i.e. root_context). 263 * --------------------------------------------------------------------- 264 */ 265 setup_el3_execution_context 266 267 .if \_secondary_cold_boot 268 /* ------------------------------------------------------------- 269 * Check if this is a primary or secondary CPU cold boot. 270 * The primary CPU will set up the platform while the 271 * secondaries are placed in a platform-specific state until the 272 * primary CPU performs the necessary actions to bring them out 273 * of that state and allows entry into the OS. 274 * ------------------------------------------------------------- 275 */ 276 bl plat_is_my_cpu_primary 277 cbnz w0, do_primary_cold_boot 278 279 /* This is a cold boot on a secondary CPU */ 280 bl plat_secondary_cold_boot_setup 281 /* plat_secondary_cold_boot_setup() is not supposed to return */ 282 bl el3_panic 283 284 do_primary_cold_boot: 285 .endif /* _secondary_cold_boot */ 286 287 /* --------------------------------------------------------------------- 288 * Initialize memory now. Secondary CPU initialization won't get to this 289 * point. 290 * --------------------------------------------------------------------- 291 */ 292 293 .if \_init_memory 294 bl platform_mem_init 295 .endif /* _init_memory */ 296 297 /* --------------------------------------------------------------------- 298 * Init C runtime environment: 299 * - Zero-initialise the NOBITS sections. There are 2 of them: 300 * - the .bss section; 301 * - the coherent memory section (if any). 302 * - Relocate the data section from ROM to RAM, if required. 303 * --------------------------------------------------------------------- 304 */ 305 .if \_init_c_runtime 306#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 307 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 308 /* ------------------------------------------------------------- 309 * Invalidate the RW memory used by the BL31 image. This 310 * includes the data and NOBITS sections. This is done to 311 * safeguard against possible corruption of this memory by 312 * dirty cache lines in a system cache as a result of use by 313 * an earlier boot loader stage. If PIE is enabled however, 314 * RO sections including the GOT may be modified during 315 * pie fixup. Therefore, to be on the safe side, invalidate 316 * the entire image region if PIE is enabled. 317 * ------------------------------------------------------------- 318 */ 319#if ENABLE_PIE 320#if SEPARATE_CODE_AND_RODATA 321 adrp x0, __TEXT_START__ 322 add x0, x0, :lo12:__TEXT_START__ 323#else 324 adrp x0, __RO_START__ 325 add x0, x0, :lo12:__RO_START__ 326#endif /* SEPARATE_CODE_AND_RODATA */ 327#else 328 adrp x0, __RW_START__ 329 add x0, x0, :lo12:__RW_START__ 330#endif /* ENABLE_PIE */ 331 adrp x1, __RW_END__ 332 add x1, x1, :lo12:__RW_END__ 333 sub x1, x1, x0 334 bl inv_dcache_range 335#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 336 adrp x0, __NOBITS_START__ 337 add x0, x0, :lo12:__NOBITS_START__ 338 adrp x1, __NOBITS_END__ 339 add x1, x1, :lo12:__NOBITS_END__ 340 sub x1, x1, x0 341 bl inv_dcache_range 342#endif 343#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 344 adrp x0, __BL2_NOLOAD_START__ 345 add x0, x0, :lo12:__BL2_NOLOAD_START__ 346 adrp x1, __BL2_NOLOAD_END__ 347 add x1, x1, :lo12:__BL2_NOLOAD_END__ 348 sub x1, x1, x0 349 bl inv_dcache_range 350#endif 351#endif 352#if defined(IMAGE_BL31) 353 adrp x0, __PER_CPU_START__ 354 add x0, x0, :lo12:__PER_CPU_START__ 355 adrp x1, __PER_CPU_END__ 356 add x1, x1, :lo12:__PER_CPU_END__ 357 sub x1, x1, x0 358#if (PLATFORM_NODE_COUNT > 1) 359 mov x9, x1 360#endif /* (PLATFORM_NODE_COUNT > 1) */ 361 bl zeromem 362#if (PLATFORM_NODE_COUNT > 1) 363 /* 364 * Zero-initialize per-cpu sections defined by the platform. 365 * Care must be taken to preserve and retain the clobbered 366 * registers. A standard around the container for per-cpu nodes 367 * is not yet defined. 368 */ 369 mov x10, #1 370 mov x11, #PLATFORM_NODE_COUNT 371 372 1: 373 cmp x10, x11 374 b.hs 2f 375 376 mov x0, x10 377 bl plat_per_cpu_node_base 378 cmn x0, #1 379 b.eq 3f 380 381 /* x1 contains size param */ 382 mov x1, x9 383 bl zeromem 384 385 3: 386 add x10, x10, #1 387 b 1b 388 389 2: 390#endif /* (PLATFORM_NODE_COUNT > 1) */ 391#endif /* defined(IMAGE_BL31) */ 392 393 adrp x0, __BSS_START__ 394 add x0, x0, :lo12:__BSS_START__ 395 396 adrp x1, __BSS_END__ 397 add x1, x1, :lo12:__BSS_END__ 398 sub x1, x1, x0 399 bl zeromem 400 401#if USE_COHERENT_MEM 402 adrp x0, __COHERENT_RAM_START__ 403 add x0, x0, :lo12:__COHERENT_RAM_START__ 404 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 405 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 406 sub x1, x1, x0 407 bl zeromem 408#endif 409 410#if defined(IMAGE_BL1) || \ 411 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) || \ 412 (defined(IMAGE_BL31) && SEPARATE_RWDATA_REGION) 413 414 adrp x0, __DATA_RAM_START__ 415 add x0, x0, :lo12:__DATA_RAM_START__ 416 adrp x1, __DATA_ROM_START__ 417 add x1, x1, :lo12:__DATA_ROM_START__ 418 adrp x2, __DATA_RAM_END__ 419 add x2, x2, :lo12:__DATA_RAM_END__ 420 sub x2, x2, x0 421 bl memcpy16 422#endif 423 .endif /* _init_c_runtime */ 424 425 /* --------------------------------------------------------------------- 426 * Use SP_EL0 for the C runtime stack. 427 * --------------------------------------------------------------------- 428 */ 429 msr spsel, #0 430 431 /* --------------------------------------------------------------------- 432 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 433 * the MMU is enabled. There is no risk of reading stale stack memory 434 * after enabling the MMU as only the primary CPU is running at the 435 * moment. 436 * --------------------------------------------------------------------- 437 */ 438 bl plat_set_my_stack 439 440#if STACK_PROTECTOR_ENABLED 441 .if \_init_c_runtime 442 bl update_stack_protector_canary 443 .endif /* _init_c_runtime */ 444#endif 445 .endm 446 447 .macro apply_at_speculative_wa 448#if ERRATA_SPECULATIVE_AT 449 /* 450 * This function expects x30 has been saved. 451 * Also, save x29 which will be used in the called function. 452 */ 453 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 454 bl save_and_update_ptw_el1_sys_regs 455 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 456#endif 457 .endm 458 459 .macro restore_ptw_el1_sys_regs 460#if ERRATA_SPECULATIVE_AT 461 /* ----------------------------------------------------------- 462 * In case of ERRATA_SPECULATIVE_AT, must follow below order 463 * to ensure that page table walk is not enabled until 464 * restoration of all EL1 system registers. TCR_EL1 register 465 * should be updated at the end which restores previous page 466 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 467 * ensures that CPU does below steps in order. 468 * 469 * 1. Ensure all other system registers are written before 470 * updating SCTLR_EL1 using ISB. 471 * 2. Restore SCTLR_EL1 register. 472 * 3. Ensure SCTLR_EL1 written successfully using ISB. 473 * 4. Restore TCR_EL1 register. 474 * ----------------------------------------------------------- 475 */ 476 isb 477 ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1] 478 msr sctlr_el1, x28 479 isb 480 msr tcr_el1, x29 481#endif 482 .endm 483 484/* ----------------------------------------------------------------- 485 * The below macro reads SCR_EL3 from the context structure to 486 * determine the security state of the context upon ERET. 487 * ------------------------------------------------------------------ 488 */ 489 .macro get_security_state _ret:req, _scr_reg:req 490 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 491 cmp \_ret, #1 492 beq realm_state 493 bfi \_ret, \_scr_reg, #0, #1 494 b end 495 realm_state: 496 mov \_ret, #2 497 end: 498 .endm 499 500/*----------------------------------------------------------------------------- 501 * Helper macro to configure EL3 registers we care about, while executing 502 * at EL3/Root world. Root world has its own execution environment and 503 * needs to have its settings configured to be independent of other worlds. 504 * ----------------------------------------------------------------------------- 505 */ 506 .macro setup_el3_execution_context 507 508 /* --------------------------------------------------------------------- 509 * The following registers need to be part of separate root context 510 * as their values are of importance during EL3 execution. 511 * Hence these registers are overwritten to their intital values, 512 * irrespective of whichever world they return from to ensure EL3 has a 513 * consistent execution context throughout the lifetime of TF-A. 514 * 515 * DAIF.A: Enable External Aborts and SError Interrupts at EL3. 516 * 517 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 518 * Debug exceptions, other than Breakpoint Instruction exceptions, are 519 * disabled from all ELs in Secure state. 520 * 521 * SCR_EL3.EA: Set to one to enable SError interrupts at EL3. 522 * 523 * SCR_EL3.SIF: Set to one to disable instruction fetches from 524 * Non-secure memory. 525 * 526 * PMCR_EL0.DP: Set to one so that the cycle counter, 527 * PMCCNTR_EL0 does not count when event counting is prohibited. 528 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 529 * available. 530 * 531 * CPTR_EL3.EZ: Set to one so that accesses to ZCR_EL3 do not trap 532 * CPTR_EL3.ESM: Set to one so that SME related registers don't trap 533 * CPTR_EL3.EC: Set to one when Morello is enabled so that access to morello 534 * architecture and registers are not trapped 535 * 536 * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT) 537 * functionality, if implemented in EL3. 538 * --------------------------------------------------------------------- 539 */ 540 msr daifclr, #DAIF_ABT_BIT 541 542 mrs x15, mdcr_el3 543 orr x15, x15, #MDCR_SDD_BIT 544 msr mdcr_el3, x15 545 546 mrs x15, scr_el3 547 orr x15, x15, #SCR_EA_BIT 548 orr x15, x15, #SCR_SIF_BIT 549 bic x15, x15, #SCR_TRNDR_BIT 550 msr scr_el3, x15 551 552 mrs x15, pmcr_el0 553 orr x15, x15, #PMCR_EL0_DP_BIT 554 msr pmcr_el0, x15 555 556 mrs x15, cptr_el3 557 orr x15, x15, #CPTR_EZ_BIT 558 orr x15, x15, #ESM_BIT 559#if ENABLE_FEAT_MORELLO 560 orr x15, x15, #EC_BIT 561#endif /* ENABLE_FEAT_MORELLO */ 562 msr cptr_el3, x15 563 564#if ENABLE_FEAT_DIT 565#if ENABLE_FEAT_DIT > 1 566 mrs x15, id_aa64pfr0_el1 567 ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 568 cbz x15, 1f 569#endif 570 mov x15, #DIT_BIT 571 msr DIT, x15 572 1: 573#endif 574 575 isb 576 .endm 577 578#endif /* EL3_COMMON_MACROS_S */ 579