1/* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * --------------------------------------------------------------------- 36 */ 37 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 38 mrs x0, sctlr_el3 39 orr x0, x0, x1 40 msr sctlr_el3, x0 41 isb 42 43#ifdef IMAGE_BL31 44 /* --------------------------------------------------------------------- 45 * Initialise the per-cpu cache pointer to the CPU. 46 * This is done early to enable crash reporting to have access to crash 47 * stack. Since crash reporting depends on cpu_data to report the 48 * unhandled exception, not doing so can lead to recursive exceptions 49 * due to a NULL TPIDR_EL3. 50 * --------------------------------------------------------------------- 51 */ 52 bl init_cpu_data_ptr 53#endif /* IMAGE_BL31 */ 54 55 /* --------------------------------------------------------------------- 56 * Initialise SCR_EL3, setting all fields rather than relying on hw. 57 * All fields are architecturally UNKNOWN on reset. The following fields 58 * do not change during the TF lifetime. The remaining fields are set to 59 * zero here but are updated ahead of transitioning to a lower EL in the 60 * function cm_init_context_common(). 61 * 62 * SCR_EL3.SIF: Set to one to disable instruction fetches from 63 * Non-secure memory. 64 * 65 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 66 * to EL3 when executing at any EL. 67 * --------------------------------------------------------------------- 68 */ 69 mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) 70 msr scr_el3, x0 71 72 /* --------------------------------------------------------------------- 73 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 74 * Some fields are architecturally UNKNOWN on reset. 75 * 76 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 77 * Debug exceptions, other than Breakpoint Instruction exceptions, are 78 * disabled from all ELs in Secure state. 79 * 80 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 81 * privileged debug from S-EL1. 82 * 83 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 84 * access to the powerdown debug registers do not trap to EL3. 85 * 86 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 87 * debug registers, other than those registers that are controlled by 88 * MDCR_EL3.TDOSA. 89 */ 90 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 91 MDCR_SPD32(MDCR_SPD32_DISABLE)) & \ 92 ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT)) 93 94 msr mdcr_el3, x0 95 96 /* --------------------------------------------------------------------- 97 * Enable External Aborts and SError Interrupts now that the exception 98 * vectors have been setup. 99 * --------------------------------------------------------------------- 100 */ 101 msr daifclr, #DAIF_ABT_BIT 102 103 /* --------------------------------------------------------------------- 104 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 105 * All fields are architecturally UNKNOWN on reset. 106 * --------------------------------------------------------------------- 107 */ 108 mov_imm x0, CPTR_EL3_RESET_VAL 109 msr cptr_el3, x0 110 111 /* 112 * If Data Independent Timing (DIT) functionality is implemented, 113 * always enable DIT in EL3. 114 * First assert that the FEAT_DIT build flag matches the feature id 115 * register value for DIT. 116 */ 117#if ENABLE_FEAT_DIT 118#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1 119 mrs x0, id_aa64pfr0_el1 120 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 121#if ENABLE_FEAT_DIT > 1 122 cbz x0, 1f 123#else 124 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 125 ASM_ASSERT(eq) 126#endif 127 128#endif /* ENABLE_ASSERTIONS */ 129 mov x0, #DIT_BIT 130 msr DIT, x0 1311: 132#endif 133 .endm 134 135/* ----------------------------------------------------------------------------- 136 * This is the super set of actions that need to be performed during a cold boot 137 * or a warm boot in EL3. This code is shared by BL1 and BL31. 138 * 139 * This macro will always perform reset handling, architectural initialisations 140 * and stack setup. The rest of the actions are optional because they might not 141 * be needed, depending on the context in which this macro is called. This is 142 * why this macro is parameterised ; each parameter allows to enable/disable 143 * some actions. 144 * 145 * _init_sctlr: 146 * Whether the macro needs to initialise SCTLR_EL3, including configuring 147 * the endianness of data accesses. 148 * 149 * _warm_boot_mailbox: 150 * Whether the macro needs to detect the type of boot (cold/warm). The 151 * detection is based on the platform entrypoint address : if it is zero 152 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 153 * this macro jumps on the platform entrypoint address. 154 * 155 * _secondary_cold_boot: 156 * Whether the macro needs to identify the CPU that is calling it: primary 157 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 158 * the platform initialisations, while the secondaries will be put in a 159 * platform-specific state in the meantime. 160 * 161 * If the caller knows this macro will only be called by the primary CPU 162 * then this parameter can be defined to 0 to skip this step. 163 * 164 * _init_memory: 165 * Whether the macro needs to initialise the memory. 166 * 167 * _init_c_runtime: 168 * Whether the macro needs to initialise the C runtime environment. 169 * 170 * _exception_vectors: 171 * Address of the exception vectors to program in the VBAR_EL3 register. 172 * 173 * _pie_fixup_size: 174 * Size of memory region to fixup Global Descriptor Table (GDT). 175 * 176 * A non-zero value is expected when firmware needs GDT to be fixed-up. 177 * 178 * ----------------------------------------------------------------------------- 179 */ 180 .macro el3_entrypoint_common \ 181 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 182 _init_memory, _init_c_runtime, _exception_vectors, \ 183 _pie_fixup_size 184 185 .if \_init_sctlr 186 /* ------------------------------------------------------------- 187 * This is the initialisation of SCTLR_EL3 and so must ensure 188 * that all fields are explicitly set rather than relying on hw. 189 * Some fields reset to an IMPLEMENTATION DEFINED value and 190 * others are architecturally UNKNOWN on reset. 191 * 192 * SCTLR.EE: Set the CPU endianness before doing anything that 193 * might involve memory reads or writes. Set to zero to select 194 * Little Endian. 195 * 196 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 197 * force all memory regions that are writeable to be treated as 198 * XN (Execute-never). Set to zero so that this control has no 199 * effect on memory access permissions. 200 * 201 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 202 * 203 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 204 * 205 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 206 * safe behaviour upon exception entry to EL3. 207 * ------------------------------------------------------------- 208 */ 209 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 210 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 211#if ENABLE_FEAT_RAS 212 /* If FEAT_RAS is present assume FEAT_IESB is also present */ 213 orr x0, x0, #SCTLR_IESB_BIT 214#endif 215 msr sctlr_el3, x0 216 isb 217 .endif /* _init_sctlr */ 218 219 .if \_warm_boot_mailbox 220 /* ------------------------------------------------------------- 221 * This code will be executed for both warm and cold resets. 222 * Now is the time to distinguish between the two. 223 * Query the platform entrypoint address and if it is not zero 224 * then it means it is a warm boot so jump to this address. 225 * ------------------------------------------------------------- 226 */ 227 bl plat_get_my_entrypoint 228 cbz x0, do_cold_boot 229 br x0 230 231 do_cold_boot: 232 .endif /* _warm_boot_mailbox */ 233 234 .if \_pie_fixup_size 235#if ENABLE_PIE 236 /* 237 * ------------------------------------------------------------ 238 * If PIE is enabled fixup the Global descriptor Table only 239 * once during primary core cold boot path. 240 * 241 * Compile time base address, required for fixup, is calculated 242 * using "pie_fixup" label present within first page. 243 * ------------------------------------------------------------ 244 */ 245 pie_fixup: 246 ldr x0, =pie_fixup 247 and x0, x0, #~(PAGE_SIZE_MASK) 248 mov_imm x1, \_pie_fixup_size 249 add x1, x1, x0 250 bl fixup_gdt_reloc 251#endif /* ENABLE_PIE */ 252 .endif /* _pie_fixup_size */ 253 254 /* --------------------------------------------------------------------- 255 * Set the exception vectors. 256 * --------------------------------------------------------------------- 257 */ 258 adr x0, \_exception_vectors 259 msr vbar_el3, x0 260 isb 261 262#if !(defined(IMAGE_BL2) && ENABLE_RME) 263 /* --------------------------------------------------------------------- 264 * It is a cold boot. 265 * Perform any processor specific actions upon reset e.g. cache, TLB 266 * invalidations etc. 267 * --------------------------------------------------------------------- 268 */ 269 bl reset_handler 270#endif 271 272 el3_arch_init_common 273 274 .if \_secondary_cold_boot 275 /* ------------------------------------------------------------- 276 * Check if this is a primary or secondary CPU cold boot. 277 * The primary CPU will set up the platform while the 278 * secondaries are placed in a platform-specific state until the 279 * primary CPU performs the necessary actions to bring them out 280 * of that state and allows entry into the OS. 281 * ------------------------------------------------------------- 282 */ 283 bl plat_is_my_cpu_primary 284 cbnz w0, do_primary_cold_boot 285 286 /* This is a cold boot on a secondary CPU */ 287 bl plat_secondary_cold_boot_setup 288 /* plat_secondary_cold_boot_setup() is not supposed to return */ 289 bl el3_panic 290 291 do_primary_cold_boot: 292 .endif /* _secondary_cold_boot */ 293 294 /* --------------------------------------------------------------------- 295 * Initialize memory now. Secondary CPU initialization won't get to this 296 * point. 297 * --------------------------------------------------------------------- 298 */ 299 300 .if \_init_memory 301 bl platform_mem_init 302 .endif /* _init_memory */ 303 304 /* --------------------------------------------------------------------- 305 * Init C runtime environment: 306 * - Zero-initialise the NOBITS sections. There are 2 of them: 307 * - the .bss section; 308 * - the coherent memory section (if any). 309 * - Relocate the data section from ROM to RAM, if required. 310 * --------------------------------------------------------------------- 311 */ 312 .if \_init_c_runtime 313#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 314 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 315 /* ------------------------------------------------------------- 316 * Invalidate the RW memory used by the BL31 image. This 317 * includes the data and NOBITS sections. This is done to 318 * safeguard against possible corruption of this memory by 319 * dirty cache lines in a system cache as a result of use by 320 * an earlier boot loader stage. If PIE is enabled however, 321 * RO sections including the GOT may be modified during 322 * pie fixup. Therefore, to be on the safe side, invalidate 323 * the entire image region if PIE is enabled. 324 * ------------------------------------------------------------- 325 */ 326#if ENABLE_PIE 327#if SEPARATE_CODE_AND_RODATA 328 adrp x0, __TEXT_START__ 329 add x0, x0, :lo12:__TEXT_START__ 330#else 331 adrp x0, __RO_START__ 332 add x0, x0, :lo12:__RO_START__ 333#endif /* SEPARATE_CODE_AND_RODATA */ 334#else 335 adrp x0, __RW_START__ 336 add x0, x0, :lo12:__RW_START__ 337#endif /* ENABLE_PIE */ 338 adrp x1, __RW_END__ 339 add x1, x1, :lo12:__RW_END__ 340 sub x1, x1, x0 341 bl inv_dcache_range 342#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 343 adrp x0, __NOBITS_START__ 344 add x0, x0, :lo12:__NOBITS_START__ 345 adrp x1, __NOBITS_END__ 346 add x1, x1, :lo12:__NOBITS_END__ 347 sub x1, x1, x0 348 bl inv_dcache_range 349#endif 350#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 351 adrp x0, __BL2_NOLOAD_START__ 352 add x0, x0, :lo12:__BL2_NOLOAD_START__ 353 adrp x1, __BL2_NOLOAD_END__ 354 add x1, x1, :lo12:__BL2_NOLOAD_END__ 355 sub x1, x1, x0 356 bl inv_dcache_range 357#endif 358#endif 359 adrp x0, __BSS_START__ 360 add x0, x0, :lo12:__BSS_START__ 361 362 adrp x1, __BSS_END__ 363 add x1, x1, :lo12:__BSS_END__ 364 sub x1, x1, x0 365 bl zeromem 366 367#if USE_COHERENT_MEM 368 adrp x0, __COHERENT_RAM_START__ 369 add x0, x0, :lo12:__COHERENT_RAM_START__ 370 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 371 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 372 sub x1, x1, x0 373 bl zeromem 374#endif 375 376#if defined(IMAGE_BL1) || \ 377 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) 378 adrp x0, __DATA_RAM_START__ 379 add x0, x0, :lo12:__DATA_RAM_START__ 380 adrp x1, __DATA_ROM_START__ 381 add x1, x1, :lo12:__DATA_ROM_START__ 382 adrp x2, __DATA_RAM_END__ 383 add x2, x2, :lo12:__DATA_RAM_END__ 384 sub x2, x2, x0 385 bl memcpy16 386#endif 387 .endif /* _init_c_runtime */ 388 389 /* --------------------------------------------------------------------- 390 * Use SP_EL0 for the C runtime stack. 391 * --------------------------------------------------------------------- 392 */ 393 msr spsel, #0 394 395 /* --------------------------------------------------------------------- 396 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 397 * the MMU is enabled. There is no risk of reading stale stack memory 398 * after enabling the MMU as only the primary CPU is running at the 399 * moment. 400 * --------------------------------------------------------------------- 401 */ 402 bl plat_set_my_stack 403 404#if STACK_PROTECTOR_ENABLED 405 .if \_init_c_runtime 406 bl update_stack_protector_canary 407 .endif /* _init_c_runtime */ 408#endif 409 .endm 410 411 .macro apply_at_speculative_wa 412#if ERRATA_SPECULATIVE_AT 413 /* 414 * This function expects x30 has been saved. 415 * Also, save x29 which will be used in the called function. 416 */ 417 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 418 bl save_and_update_ptw_el1_sys_regs 419 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 420#endif 421 .endm 422 423 .macro restore_ptw_el1_sys_regs 424#if ERRATA_SPECULATIVE_AT 425 /* ----------------------------------------------------------- 426 * In case of ERRATA_SPECULATIVE_AT, must follow below order 427 * to ensure that page table walk is not enabled until 428 * restoration of all EL1 system registers. TCR_EL1 register 429 * should be updated at the end which restores previous page 430 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 431 * ensures that CPU does below steps in order. 432 * 433 * 1. Ensure all other system registers are written before 434 * updating SCTLR_EL1 using ISB. 435 * 2. Restore SCTLR_EL1 register. 436 * 3. Ensure SCTLR_EL1 written successfully using ISB. 437 * 4. Restore TCR_EL1 register. 438 * ----------------------------------------------------------- 439 */ 440 isb 441 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 442 msr sctlr_el1, x28 443 isb 444 msr tcr_el1, x29 445#endif 446 .endm 447 448/* ----------------------------------------------------------------- 449 * The below macro reads SCR_EL3 from the context structure to 450 * determine the security state of the context upon ERET. 451 * ------------------------------------------------------------------ 452 */ 453 .macro get_security_state _ret:req, _scr_reg:req 454 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 455 cmp \_ret, #1 456 beq realm_state 457 bfi \_ret, \_scr_reg, #0, #1 458 b end 459 realm_state: 460 mov \_ret, #2 461 end: 462 .endm 463 464#endif /* EL3_COMMON_MACROS_S */ 465